Three-dimensional chip integration structure and machining process thereof
A three-dimensional chip and processing technology, applied in electrical components, electrical solid devices, circuits, etc., can solve the problems of high manufacturing costs, high equipment requirements, and complicated processes, and achieve the effect of reducing process costs.
Inactive Publication Date: 2015-05-20
NAT CENT FOR ADVANCED PACKAGING
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Problems solved by technology
TSV technology needs to go through a series of process steps such as deep hole etching, insulating layer deposition, seed layer deposition, electroplating, and chemical mechanical polishing. The process is cumbersome, the manufacturing cost is high, and the requirements for equipment are high. one
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[0019] The present invention will be further described according to the accompanying drawings,
[0020] See figure 1 , figure 2 , a three-dimensional chip integration structure, which includes a substrate 7, the interposer 4 is connected to the substrate 7 through solder balls or bumps 5, the chip 1 is connected to the interposer 4 through the first metal pad or the first bump 3, and the substrate 7 A plurality of metal pillar structures 6 are arranged on it, and the chip 1 is connected to the metal pillar structures 6 through a second metal pad or a second bump 8 .
[0021] Two adapter boards 4 are respectively connected to the substrate 7 through solder balls or bumps 5 to realize the interconnection between two chips and the substrate. In this embodiment, two chips 1 and 2 are used to realize two The interconnection between the chip and the substrate, of course, can use multiple numbers of chips to interconnect with the adapter board, or use other numbers of multiple ada...
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The invention provides a three-dimensional chip integration structure, which has the advantages of simple structure, low manufacturing process requirement, reduction of TSV (Through Silicon Via) manufacturing process steps and well lowering of the process cost. The three-dimensional chip integration structure comprises a substrate, and is characterized in that an adapting board is connected with the substrate through welding balls or salient points; the chip is connected with the adapting board through a first metal bonding pad or a first salient point; the substrate is provided with a metal column structure; the chip is connected with the metal column structure through a second metal bonding pad or a second salient point. The invention simultaneously provides a three-dimensional chip integration structure machining process.
Description
technical field [0001] The invention relates to the technical field of microelectronics manufacturing or processing methods for semiconductor or solid devices, in particular to a three-dimensional chip integrated structure and its processing technology. Background technique [0002] With the continuous advancement of microelectronics technology, the feature size of integrated circuits has been continuously reduced and the interconnection density has been continuously increased. At the same time, users' requirements for high performance and low power consumption continue to increase. In this case, the way to improve the performance by further reducing the line width of the interconnection is limited by the physical characteristics of the material and the equipment process, and the resistance-capacitance (RC) delay of the two-dimensional interconnection gradually becomes the limit to improve the performance of the semiconductor chip. bottleneck. The Through Silicon Via (TSV)...
Claims
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IPC IPC(8): H01L23/488H01L23/535H01L21/60
CPCH01L2224/73203H01L2224/81192H01L2224/92143
Inventor 靖向萌
Owner NAT CENT FOR ADVANCED PACKAGING