High, depth and width three-dimensional uprightness interconnect and realization method of three-dimensional integrate circuit

Abstract

The invention discloses a method for realizing a three-dimensional vertical interconnection with a high aspect ratio and a three-dimensional integrated circuit, which belong to the technical fields of semiconductor manufacturing technology and micro sensor manufacturing technology. The method includes: performing deep reactive ion etching on the front surface of a semiconductor wafer with a planar integrated circuit or a micro sensor to obtain a deep hole; depositing an insulating layer, a diffusion barrier layer and an electroplating seed layer on the front surface; The electroplating surface is temporarily bonded to the auxiliary wafer, and the back of the semiconductor wafer is thinned so that the DRIE deep hole is exposed from the back; an insulating layer, a diffusion barrier layer, and an electroplating seed layer are deposited on the back; a bottom-up electroplating process is performed, and the The DRIE deep hole is filled to form a high aspect ratio three-dimensional vertical interconnection; the auxiliary wafer is removed to realize the vertical integration of two-layer wafers; the above steps are repeated to realize more layers of three-dimensional integrated circuits. The invention reduces the process difficulty of filling through holes with high aspect ratio. The manufacturing process is simplified and the yield rate is guaranteed.

Description

technical field [0001] The invention belongs to the technical field of semiconductor and micro-sensor manufacturing, and in particular relates to a high-aspect-ratio three-dimensional vertical interconnect and a method for realizing a three-dimensional integrated circuit using the three-dimensional integrated circuit manufacturing technology. Background technique [0002] The continuous shrinking of integrated circuit devices has continuously improved the integration level. At present, more than 1 billion transistors can be integrated on a chip area per square centimeter, and the total length of metal interconnection lines reaches tens of kilometers. This not only makes the wiring extremely complicated, but more importantly, the delay, power consumption, and noise of the metal interconnection increase with the reduction of the feature size, especially the RC delay of the global interconnection, which seriously affects the integrated circuit. performance. In addition, the dy...

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Problems solved by technology

This method is easy to fill through holes, but in order to ensure the operability of the semiconductor wafer, the thickness of a single-layer semiconductor wafer is often more than 200 microns, even if the aspect ratio of the vertical interconnection line is as high as 20, the lateral dimension of the interconnection line is too large. Above 10 microns, limits the improvement of interconnect line density

[0008] One solution is to make an electroplating seed layer on the front side of the semiconductor wafer, and then conduct a thinning treatment on the semiconductor wafer through temporary bonding of the auxiliary wafer, and then perform deep reactive ion etching (DRIE) to obtain a deep hole, then deposit the insulating layer and selectively etch the insulating layer at the bottom of the hole to maintain the insulating effect of the side wall, and finally adopt the bottom-up electroplating method to obtain high-density vertical interconnection. This method corresponds to The problem is that during deep etching, lateral undercutting will occur at the position of the seed layer, which is difficult to control. In addition, the growth of the insulating layer on the side wall of the deep hole is very difficult, and in addition to the selective etching after one-step growth, it is difficult to ensure mutual Insulation effect of wiring to substrate

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