Wafer thinning method and wafer structure

Abstract

The present invention provides a wafer thinning method and a wafer structure. The embodiment of the present application provides a wafer thinning method. After providing the wafer to be thinned, it can be ground from the back of the wafer, and then the The first planarization process is performed on the back of the wafer to repair the flatness of the wafer after grinding, and then the second planarization process is performed from the back of the wafer until the target thinning thickness is reached. That is to say, the embodiment of the present application can repair the flatness of the wafer through two planarization processes after removing part of the thickness of the wafer, without using an epitaxial layer as an etching stop layer, which reduces the cost of thinning, while Grinding removes most of the thickness without using acid etching, avoiding the lateral undercutting caused by acid etching, thereby reducing the number of edge trimmings caused by lateral undercutting and increasing the effective chip area.

Description

Technical field [0001] The present invention relates to a semiconductor device and a manufacturing range thereof, and more particularly to a thin wafer thinning method and a wafer structure. Background technique [0002] With the continuous development of semiconductor technology, 3D-IC (3D integrated circuit) technology has been widely used, which use wafer level packaging technology to combine different wafers, which has high performance, low cost. And the advantage of high integration. [0003] In the implementation of the wafer stage package technology, after the wafer bond, thinned from the back surface of the wafer, in order to obtain a flat surface after thinning, EPI (Epitaxy, epitaxial) wafer is usually used, ie in silicon The wafer of the epitaxial layer is grown on the substrate, and during thinning, the epitaxial layer is etched as an acid method, so that the flat silicon surface can be obtained, however, the wafer of the EPI is high, and In the process of etching, th...

AI Technical Summary

Problems solved by technology

[0003] In the implementation of wafer-level packaging technology, after wafer bonding, thinning is carried out from the back of the wafer. In order to obtain a flat surface after thinning, an EPI (Epitaxy, epitaxial) wafer is usually used, that is, on silicon A wafer with an epitaxial layer grown on the substrate. During the thinning process, the epitaxial layer is used as a stop layer for acid etching, so that a flat silicon surface can be obtained. During the etching process of the wafer, it will cause undercutting in the lateral direction of the wafer, which needs to be trimmed by cutting the edge, which will reduce the effective chip area

Images