Automatic generating device for module-level UVM (unified voltage modulation) verification platform based on AMBA bus

Abstract

The invention discloses an automatic generating device for a module-level UVM (unified voltage modulation) verification platform based on an AMBA bus. The automatic generating device comprises an option analyzer, a UVM register module generator, an interface verification component generator, a module verification component, a UVM test case generator, a UVM verification platform generator and a UVM test script generator. By inputting a module name, an AMBA bus type, other interface bus names and module register lists, the device can automatically generate the module-level UVM verification platform. The automatic generating device reduces requirements of the complex UVM verification method to a user, shortens a required period for establishing the module-level UVM verification platform and greatly improves the module verification quality and efficiency.

Description

technical field [0001] The invention relates to the field of integrated circuit design function verification and verification methodology, in particular to an automatic generation device for a module-level UVM (Universal Verification Methodology) verification platform based on AMBA (Advanced Microcontroller Bus Architecture) bus. Background technique [0002] With the advancement of VLSI technology, the complexity of SOC (system-on-chip) design continues to increase, and IP (intellectual property) core multiplexing has become a very important part of SOC design. Quality also puts forward higher requirements, thus promoting the continuous development of verification methodologies. [0003] Starting from a verification methodology eRM (e Reusable Methodology) announced by Verisity in 2002, Synopsys (Synopsys) announced the Reusable Verification Methodology Library (RVM) in 2003, and Mentor (Mentor) Corporation in 2006 Published the Advanced Verification Methodology (AVM). In ...

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Problems solved by technology

[0004] However, the UVM verification methodology itself introduces a large number of new concepts and new processes, especially for beginners, it is quite difficult to understand and establish a verification platform that meets the UVM standard in a short time

In particular, although UVM has become a verification standard, the tool usage and processes provided by different EAD (electronic design automation) manufacturers are still quite different.

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