Semiconductor electrostatic discharge protection device

Abstract

The invention discloses a semiconductor electrostatic discharge protection device, which comprises a first electric transistor, a second electric trap region, a second electric protection ring and a semiconductor separation region, wherein the first electric transistor is formed in the second electric trap region, the second electric protection ring surrounds the first electric transistor, the semiconductor separation region is positioned between the first electric transistor and the second electric protection ring, and surrounds the first electric transistor, and in addition, the semiconductor separation region is a non-doping region, a first electric doping region or a second electric doping region with the doping concentration being smaller than that of the second electric trap region.

Description

technical field [0001] The invention relates to a semiconductor integrated circuit element, and in particular to a semiconductor electrostatic discharge protection device. Background technique [0002] Electrostatic discharge is the migration of electrostatic charges on non-conductive surfaces through conductive materials. Since electrostatic voltage is usually quite high, electrostatic discharge can easily damage the substrate and other components of an integrated circuit. In order to protect the integrated circuit from being damaged by ESD, a device with the function of conducting the ESD current to the ground is integrated into the integrated circuit. [0003] Take the grounded gate n-type metal-oxide-semiconductor conductor Gate Grounded n-type Metal-Oxide-Semiconductor (GGNMOS) transistor unit as an example, its gate, source and element substrate are grounded, when electrostatic discharge occurs (ESD zapping) , the snapback causes the grounded gate n-type metal-oxide-...

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Problems solved by technology

[0004] However, the traditional grounded gate n-type metal-oxide-semiconductor transistor unit is prone to secondary snapback collapse due to the base push-out effect of the parasitic NPN bicarrier junction transistor. To make the excessive leakage current pass through the emitter and ground base of the parasitic double carrier junction transistor, and then conduct to the ground f...

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