FPGA (Field Programmable Gate Array) single-particle overturning soft error detection method based on redundancy interconnection resources

Abstract

The invention discloses an FPGA (Field Programmable Gate Array) single-particle overturning soft error detection method based on redundancy interconnection resources. The FPGA single-particle overturning soft error detection method comprises the following steps: step 1, establishing a connection relation in interconnection resources in an FPGA; step 2, not using a logic unit and directly inserting a comparing circuit into an FPGA device; step 3, finding a copying line for the existing interconnection resources; and step 4, combining the copying line and the comparing circuit to carry out dual backup comparison on the FPGA based on the redundancy interconnection resources so as to realize error detection. By the aid of the FPGA single-particle overturning soft error detection method, a phenomenon that more redundancy exists in the interconnection resources of the design is sufficiently designed, and an efficient redundancy interconnection resource search algorithm is explored; an FPGA structure is simply modified so that the efficient online detection on single-particle overturning soft errors is realized.

Description

technical field [0001] The invention relates to the field of FPGA soft error protection and detection, in particular to an FPGA single event flip soft error detection method based on redundant interconnection resources. Background technique [0002] At present, most FPGA devices use SRAM, that is, Static Random Access Memory (SRAM), as a storage unit for configuration information. Although SRAM-type FPGA devices have the advantages of short development cycle, low cost, high performance, low power consumption, and reconfigurability, a large number of SRAM configurable cells in SRAM-type FPGA devices are extremely vulnerable to high-energy particles and single event upsets ( Single Event Upset (SEU) soft error, which makes its structure and function change and cause function failure. With the continuous improvement of device integration and the continuous expansion of the application range of FPGA devices, the reliability problems caused by single event upset soft errors have...

AI Technical Summary

Problems solved by technology

[0005] The essence of DWC technology is a detection technology based on hardware redundancy, which needs to provide comprehensive redundancy for various hardware resources such as sequential components, combinational logic, wiring resources, and I / O ports for the circuit, but the comprehensive redundancy strategy will lead to DWC Technology has significant overhead in terms of area, timing, power consumption, and I / O ports

At the same time, the internal resource occupancy rate of FPGA often has a large difference. This kind of unbalanced resource occupancy phenomenon is very common in actual design. Often due to the limitation of certain resources, it cannot realize the complete dual backup comparison technology.

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