Pseudo gate removing method

Abstract

The invention provides a pseudo gate removing method. In a pseudo gate removing step, pulse plasma etching is adopted to conduct first etching on a pseudo gate, and then second etching is conducted on the residual pseudo gate. When the pulse plasma etching is adopted to conduct the first etching on the pseudo gate, an etching machine outputs source power in a pulse mode to etch the pseudo gate in an intermittent mode, source power output time and vacant time are both short, a polymer and solid produced in etching are discharged out of an opening formed through etching within the interval time of source power vacancy, the pulse plasma etching rates adopted for pseudo gates different in size are equal under the condition that no polymer blockage exists, a gate electrode dielectric layer with large-sized pseudo gates can be kept in a good shape when first etching is completed, and further the performance of the gate electrode dielectric layer can be improved.

Description

technical field [0001] The invention relates to the field of semiconductors, in particular to a method for removing dummy gates. Background technique [0002] In the high-K dielectric / metal gate engineering of transistors, after high-temperature annealing for ion activation, the dummy gate (such as polysilicon gate) needs to be removed, and then the metal gate is filled to form a high-K dielectric / metal gate structure . [0003] refer to figure 1 and figure 2 , shows a method for removing dummy gates in the prior art. Such as figure 1 As shown in the first dummy gate structure 20A and the second dummy gate structure 20B in the substrate 01, the first dummy gate structure 20A includes the first dummy gate 12A and the first gate dielectric layer at the bottom of the first dummy gate 12A 11A, the first spacer 13A on the side wall of the first dummy gate 12A; the second dummy gate structure 20B includes the second dummy gate 12B, the second gate dielectric layer 11B at the...

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Problems solved by technology

Therefore, if figure 2 As shown, when the first dummy gate 12A with a smaller size is etched clean, the dummy gate of the second dummy gate 12B with a larger size has already been removed to expose the second gate dielectric layer 11B prematurely. The gate dielectric layer 11B is damaged by plasma etching, and after the metal gate is filled in the opening, the insulation between the metal gate and the substrate 10 is poor

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