Method of preparing on-insulator material with accurate and controllable stripping position

An insulator and precise technology, which is applied in the field of preparation of materials on insulators, can solve the problems of rough peeling surface, inaccurate control of peeling position, large implantation dose, etc., and achieve the goal of reducing damage, small ion implantation dose, and precise control of peeling position Effect

Active Publication Date: 2015-07-01
SHANGHAI INST OF MICROSYSTEM & INFORMATION TECH CHINESE ACAD OF SCI
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0006] In view of the above-mentioned shortcomings of the prior art, the purpose of the present invention is to provide a method for preparing a material on an insulator with precise and controllable peeling position, which is used to solve the problem of large injection dose, rough peeling surface and uneven peeling position in the prior art. problems that can be precisely controlled

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  • Method of preparing on-insulator material with accurate and controllable stripping position
  • Method of preparing on-insulator material with accurate and controllable stripping position
  • Method of preparing on-insulator material with accurate and controllable stripping position

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Embodiment 1

[0046] Such as Figure 1 to Figure 6 As shown, the present invention provides a method for preparing a material on an insulator with precise and controllable peeling positions, which at least includes the following steps:

[0047] S1: Provide a Si substrate, and epitaxially grow a doped single crystal layer on the surface of the Si substrate; the thickness of the doped single crystal layer is greater than 15 nm;

[0048]S2: epitaxially growing a single crystal thin film on the surface of the doped single crystal layer;

[0049] S3: forming a SiO on the surface of the single crystal thin film 2 Floor;

[0050] S4: from the SiO 2 Ion implantation is performed on the front side of the layer so that the ion peaks are distributed in the SiO 2 Within the preset range below the layer;

[0051] S5: Provide a substrate with an insulating layer on the surface, combine the insulating layer on the surface of the substrate with the SiO on the surface of the single crystal thin film 2...

Embodiment 2

[0070] This embodiment adopts basically the same technical solution as that of Embodiment 1, except that the ion implantation position is different from the stripping position.

[0071] See first Figure 1 to Figure 3 , and perform steps S1 to S3 that are basically the same as those in Embodiment 1. For details, refer to Embodiment 1, which will not be repeated here.

[0072] then see Figure 7 , execute step S4: from the SiO 2 Ion implantation is performed on the front side of layer 4 so that the ion peaks are distributed in the SiO 2 Within the preset range below layer 4.

[0073] Specifically, H, He or H / He is used for ion implantation, and the ion implantation dose ranges from 1E16 to 5E16 cm -2 . In this embodiment, H element is preferably used for ion implantation, and the implantation dose is 3E16cm -2 .

[0074] In this embodiment, by controlling the implantation energy E to satisfy 21keV

Embodiment 3

[0083] This embodiment adopts basically the same technical solution as that of Embodiment 1, except that the ion implantation position is different from the stripping position.

[0084] See first Figure 1 to Figure 3 , and perform steps S1 to S3 that are basically the same as those in Embodiment 1. For details, refer to Embodiment 1, which will not be repeated here.

[0085] then see Figure 10 , execute step S4: from the SiO 2 Ion implantation is performed on the front side of layer 4 so that the ion peaks are distributed in the SiO 2 Within the preset range below layer 4.

[0086] Specifically, H, He or H / He is used for ion implantation, and the ion implantation dose ranges from 1E16 to 5E16 cm -2 . In this embodiment, H element is preferably used for ion implantation, and the implantation dose is 3E16cm -2 .

[0087] In this embodiment, by controlling the implantation energy E to satisfy 10keV

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Abstract

The invention provides a method of preparing an on-insulator material with an accurate and controllable stripping position, which comprises the following steps: S1, a Si substrate is provided, and a doped single crystal layer is grown epitaxially on the surface, wherein the thickness of the doped single crystal layer is more than 15nm; S2, a single crystal thin film is grown epitaxially on the surface of the doped single crystal layer; S3, a SiO2 layer is formed on the surface of the single crystal thin film; S4, ion injection is carried out to enable ion peaks to be distributed within a preset range below the SiO2 layer; and S5, a substrate whose surface is provided with an insulated layer is provided to be bonded with the SiO2 layer on the surface of the single crystal thin film to form a bonding sheet, annealing is carried out to enable the bonding sheet to be striped at a preset position, and the on-insulator material is obtained. Effects of absorbing the injected ions by the thick doped single crystal layer are used, the injection depth is controlled, a stripping interface is the upper surface of the doped single crystal layer, or the lower surface of the doped single crystal layer, or the ion distribution peak position, and the purpose of accurately controlling the stripping position is achieved.

Description

technical field [0001] The invention belongs to the field of semiconductor manufacturing and relates to a method for preparing a material on an insulator with precise and controllable peeling positions. Background technique [0002] In recent years, materials on insulators have been widely used in many fields such as low-voltage, low-power, high-temperature, and radiation-resistant devices because of their unique insulating buried layer structure, which can reduce the parasitic capacitance and leakage current of the substrate. Making devices with smaller size and higher performance has always been the goal and direction of the development of the semiconductor industry. With the entry of VLSI technology into the 22nm node and below, higher requirements are placed on the feature size of integrated circuits. Based on ultra-thin Materials-on-insulator devices enable further device miniaturization. [0003] Usually, the preparation of materials on insulators includes the followi...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/762
CPCH01L21/76254H01L21/76259
Inventor 张苗陈达狄增峰薛忠营王刚母志强陆子同
Owner SHANGHAI INST OF MICROSYSTEM & INFORMATION TECH CHINESE ACAD OF SCI
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