A method of making a semiconductor device

Abstract

The invention discloses a method for manufacturing a semiconductor device. According to the method of the invention, a two-step process is adopted to make the metal tungsten electrode layer in the metal gate trench and the metal thin film stack layer on the side wall of the metal gate trench The first step is to remove the cover layer, barrier layer and P-type work function metal layer on the sidewall of the metal gate trench; the second step is to etch back the metal tungsten electrode layer and remove the N layer on the sidewall of the metal gate trench. type work function metal layer. According to the method of the present invention, a three-step process is also proposed to make the metal tungsten electrode layer in the metal gate trench and the metal thin film stack layer located on the side wall of the metal gate trench recessed, and the first step removes the tungsten electrode layer located on the metal gate trench. The P-type work function metal layer on the side wall of the trench; the second step removes the cover layer, barrier layer and N-type work function metal layer located on the side wall of the metal gate trench; the third step etches back the metal tungsten electrode layer.

Description

technical field [0001] The present invention relates to a semiconductor manufacturing process, and in particular to an etch-back removal of part of the metal gate in FinFET's high-K / metal gate technology to form a contact hole etch stop layer on the etched remaining metal gate Methods. Background technique [0002] The main device in integrated circuits (ICs), especially VLSIs, is metal-oxide-semiconductor field-effect transistors (MOS). With the increasing maturity of semiconductor integrated circuit technology and the rapid development of VLSIs, higher High performance and more functional integrated circuits require greater component density, and the size, size, and space of individual components, between components, or by themselves need to be further reduced. For CMOS with more advanced technology nodes, high-k and metal gate last (high-k and metal gate last) technology has been widely used in CMOS devices to avoid damage to devices caused by high-temperature processing...

AI Technical Summary

Problems solved by technology

Traditional planar semiconductor device technology is physically limited and it is difficult to meet the performance of semiconductor devices with narrowed trenches, but the tri-gate process in FinFET technology can achieve good device performance

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