Heterogeneous confusion hierarchical memory device

Abstract

Provided is a heterogeneous confusion hierarchical memory device, comprising a memory controller, a buffer formed by a DRAM device, and a confusion expansion storage formed by a PCM non-volatile memory and a FLASH non-volatile memory. The confusion expansion storage can be subjected to capacity expansion by increasing the PCM non-volatile memory and the FLASH non-volatile memory. The device provided by the present invention can effectively expand a memory in a heterogeneous confusion system architecture.

Description

technical field [0001] The invention relates to computer storage technology, in particular to a heterogeneous hybrid hierarchical memory device. Background technique [0002] The process of traditional memory DRAM is very mature, and the reliability is also very stable. However, with the reduction of process technology, DRAM will face scalability problems. Compared with DRAM, the new non-volatile memory device has obvious advantages. The new non-volatile memory device represented by PCM has good scalability, and its theoretical minimum feature size is 5-8nm, which is much smaller than DRAM. And it has low static power consumption; but its read and write delay, especially the write delay is relatively large, and the number of writes is limited. [0003] The current memory system organization structure is specially designed for DRAM which is volatile, has small reading and writing differences, and has no life problem, but this system organization structure is not suitable fo...

AI Technical Summary

Problems solved by technology

Compared with DRAM, new non-volatile memory devices have obvious advantages. The new non-volatile memory devices represented by PCM have good scalability, and their theoretical minimum feature size is 5-8nm, which is much smaller than DRAM. And has low static power consumption; but its read and write delay, especially the write delay is relatively large, and the number of writes is limited

[0003] The current memory system organization structure is designed for volatile DRAM with small reading and writing differences and no life problems, but this system organization structure is not suitable for new non-volatile memory

The current memory management methods, access interface design, memory scheduling, etc. do not consider the life of NVM, write performance, unbalanced reading and writing, etc., resulting in the above characteristics of non-volatile memory cannot be fully utilized; at the same time, the traditional memory system The organizational structure may also amplify the weaknesses of new memory devices, which is not conducive to the construction of high-performance, low-power, large-capacity heterogeneous hybrid memory systems

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