A low dropout linear regulator

Abstract

The present invention provides a low dropout linear regulator, comprising: a first P-type field effect transistor, a second P-type field effect transistor, a third P-type field effect transistor, a first N-type field effect transistor, a first resistor , low dropout linear voltage regulator enabling signal, first P-type field effect transistor enabling signal and first N-type field effect transistor enabling signal; adding a field effect transistor as a switching tube in a traditional low dropout linear voltage regulator , using the enable signal of the low dropout linear regulator to generate the enable signal of the two switch tubes, when the enable signal of the low dropout linear regulator is pulled up, the gate terminal of the P-type field effect transistor is pulled down to a suitable low voltage , to speed up the establishment process of the entire loop and reduce the voltage establishment time of the low dropout linear regulator.

Description

technical field

[0001] The invention relates to the field of electronic technology, in particular to a low-dropout linear regulator. Background technique

[0002] Traditional low dropout linear regulators such as figure 1 , including: input voltage Vref, output voltage Vout, power supply VCC, P-type field effect transistor P3, resistor R, low-dropout linear regulator enable signal LDO_EN, because the low-dropout linear regulator is applied to the comparator COMP of the flash memory, In order to save power consumption, the current of the comparator is generally relatively small and the bandwidth is relatively low, so the establishment time of the entire loop of the low dropout linear regulator is relatively long, which easily reduces the working efficiency of the flash memory. Contents of the invention

[0003] The invention provides a low-dropout linear voltage stabilizer to solve the problem that the whole loop of the low-dropout linear voltage stabilizer has relatively ...

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