Looking for breakthrough ideas for innovation challenges? Try Patsnap Eureka!

A clock control method and device

A clock control and clock technology, applied in the direction of data processing power supply, signal generation/distribution, etc., can solve problems such as increasing software complexity and affecting chip performance, achieving the effect of increasing reusability, improving processing performance, and reducing software complexity

Active Publication Date: 2018-04-13
DATANG MICROELECTRONICS TECH CO LTD
View PDF5 Cites 0 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0006] The above methods require software personnel to be very clear about the operation process, which increases the complexity of the software and affects the performance of the chip.

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • A clock control method and device
  • A clock control method and device
  • A clock control method and device

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0026] Hereinafter, the present invention will be described in detail with reference to the drawings and examples. It should be noted that, in the case of no conflict, the embodiments in the present application and the features in the embodiments can be combined with each other.

[0027] like image 3 As shown, it includes: CPU, shallow sleep register, algorithm operation module, EEPROM / flash write and erase operation module, DMA (Direct Memory Access, memory direct access) operation module, deep sleep mode, analog IP switch management, clock control device.

[0028] Pre-configure the clock control strategy in the shallow sleep register;

[0029] When the business module is running, the clock control device closes the non-working analog IP in the light sleep mode according to the clock control strategy obtained from the light sleep register;

[0030] Turning off the analog IP that does not work in shallow sleep mode includes: turning off the CPU clock, turning on the clock o...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

The present invention provides a clock control method and device. The device includes a sleep mode management module and a sleep policy execution module; The clock control strategy obtained by the register, close the analog IP that does not work in shallow sleep mode; after the business module is finished running, the clock control device obtains the clock control strategy from the shallow sleep register, and turns on the analog IP that is closed in shallow sleep mode; the sleep strategy execution module , is also used for when the deep sleep mode is started, the clock control device automatically executes off the analog IP that does not work in the deep sleep mode; the sleep policy execution module is also used for the clock control device to automatically execute when the external interrupt arrives after the deep sleep mode is started. Analog IP turned off in deep sleep mode. The invention adopts the hardware system to automatically manage the gate control clock, thereby greatly improving the processing performance.

Description

technical field [0001] The invention belongs to the field of clock control, in particular to a clock control method and device. Background technique [0002] Power consumption management has always been the key to chip development and design, and is the basis for the low-power consumption of the entire chip. A good power consumption management method can not only improve the operating speed of the entire chip, but also enable it to operate with low energy consumption and prolong the standby time. [0003] The traditional power management method is mainly realized by dividing its constituent modules into multiple clock regions, and then using the embedded software of DPM technology to manage the clock supply of each clock region, and completely shutting down the clocks of modules that do not participate in the current work input, to turn the clock supply back on when required to engage the work, [0004] like figure 1 As shown, the software configures the 1.1 register, and ...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Patents(China)
IPC IPC(8): G06F1/32G06F1/04
Inventor 刘蕊丽
Owner DATANG MICROELECTRONICS TECH CO LTD
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Patsnap Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Patsnap Eureka Blog
Learn More
PatSnap group products