Overlay mark

Abstract

The invention discloses a lamination mark, and the lamination mark comprises a front layer measurement mark formed in one layer of a semiconductor substrate or one layer of an epitaxial layer of the semiconductor substrate, and a rear layer measurement mark formed at the same position of the same layer. The lamination mark also comprises dummy patterns which are uniformly distributed in blank regions of the front and rear layer measurement marks, thereby preventing distortion caused by stress of the lamination mark from affecting measurement precision. In addition, the signal intensity of the dummy patterns is less than the signal intensity of the front and rear layer measurement marks, and can be filtered by a measurement system during the measurement and calculation of alignment precision, thereby improving the measurement precision and device yield under the condition of not affecting a conventional measurement mode.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a laminated mark. Background technique [0002] Today, with the continuous development of electronic technology, with the continuous development of Moore's Law, in order to improve the performance and speed of integrated circuits in the semiconductor industry, more and more transistors are integrated into chips. Along with this miniaturization trend, the requirements for overlay accuracy between layers are getting higher and higher. Among them, an overlay mark is usually used to measure the overlay accuracy between two layers. Specifically, refer to figure 1 , is a schematic diagram of an existing stack mark, a front-layer measurement mark 101 is formed in a certain layer of a semiconductor substrate or an epitaxial layer, and the pattern of the front-layer measurement mark 101 is a square frame surrounded by four bar graphics . Then, in the photolithograp...

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Problems solved by technology

[0003] However, in actual production, it is found that the existing stack marks will be distorted during the etching or annealing process, refer to figure 2 , is a cross-sectional schematic diagram of the distortion of the existing laminated marking graphics. After the distortion occurs, the bar pattern forming a square frame is deformed or becomes asymmetrical. The measured position of the distorted bar graphic is not the same as the actual position. Not the same, affecting the measured data, which will lead to inaccurate overlay accuracy measured and seriously affect the yield of the device

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