Method and system for implementing 10gbase-x4 PCS architecture using 20bits data interface

Abstract

The present invention provides a method and a system for implementing a 10GBase-X4 PCS architecture using a 20bits data interface, the method comprising: demarcating 20bit data in the receiving direction of data to generate new 20bit data 1; Data 1 is decoded to generate new 2-byte data; the 2-byte data is dejittered to generate new 2-byte data 1; in the direction of data transmission, the 2-byte data sent by the upper layer of the PCS is received 2. Encode the 2-byte data 2 to generate new 20-bit data 2 . The method and system for realizing the 10GBase-X4 PCS architecture by adopting the 20bits data interface of the present invention demarcate, decode, de-jitter, and encode the original data, so that its working clock is effectively reduced to the clock frequency of the traditional 10GBase-X4 PCS architecture half of that, thereby reducing the power consumption of the chip.

Description

technical field [0001] The invention relates to the field of network communication, in particular to a method and a system for realizing a 10GBase-X4PCS architecture by adopting a 20bits data interface. Background technique [0002] With the development of network technology and the popularization of informatization applications, Ethernet switches have been used more and more widely, and different application scenarios have different requirements for the port form and transmission rate of switches. [0003] Among them, 10GBase-X4 is a physical interface type defined by IEEE802.3. 10GBase-X4 PCS is composed of 4 channels. Traditional 10GBase-X4 PCS mostly adopts 10bit interface architecture. In this architecture, the rate of each channel is 3.125Gbit / s, therefore, it needs to run under the clock of 312.5MHz, the clock frequency is too high, and the power consumption of the chip is increased at the same time. Contents of the invention [0004] The purpose of the present in...

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Problems solved by technology

[0003] Among them, 10GBase-X4 is a physical interface type defined by IEEE802.3. 10GBase-X4 PCS is composed of 4 channels. Traditional 10GBase-X4 PCS mostly adopts 10bit interface architecture. In this architecture, the rate of each channel is 3.125Gbit / s, so it needs to run at 312.5MHz clock, the clock frequency is too high, and at the same time increases the power consumption of the chip

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