Method and device for exposed back side of TSV

Abstract

A method and an apparatus for TSVs reveal are provided. The method includes the following steps: providing a Si substrate (101) having a plurality of TSVs (102) formed inside the Si substrate (101); rotating the Si substrate (101) and spraying a first etchant onto th backside of the Si substrate (101) to etch the backside of the Si substrate (101), and stopping etching before the TSVs (102) being exposed to the backside of the Si substrate (101); and rotating the Si substrate (101) and spraying a second etchant onto the backside o the Si substrate (101) to etch the backside of the Si substrate (101) until the TSVs (102) being exposed to the backside of the Si substrate (101), wherein reversing the rotation direction of the Si substrate (101) at fixed intervals during spraying the second etchant onto th backside of the Si substrate (101).

Description

technical field [0001] The invention relates to a method and a device for outcropping at the back of a through-silicon hole, in particular to a method and a device for realizing the outcropping of the backside of a through-silicon hole through silicon etching. Background technique [0002] The continual reduction in VLSI dimensions reduces gate delays but rapidly increases interconnect delays. As semiconductor technology nodes continue to shrink, performance improvements in advanced VLSI have begun to saturate, where heavy interconnect loading increases power consumption in high-performance chips. Wire cross-sections are getting smaller, pitches are getting shorter, and circuits that grow across large chips add RC delays. As a result, traditional two-dimensional (2D) packaging technologies are rapidly approaching physical limits, making it very difficult to shrink the size of their devices. [0003] In recent years, three-dimensional (3D) integrated circuit physical design...

AI Technical Summary

Problems solved by technology

However, CMP still has some inherent disadvantages. For example, due to the relatively high grinding rate of the copper layer and the relatively low grinding rate of the thermal oxide layer in the CMP process, it is possible to contaminate the silicon layer with conductive materials (such as copper and tungsten) and cause Reduced device reliability, scratches, dents, corrosion, etc.

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