A clock tree synthesis method for a multi-macrocell multi-clock chip

Abstract

The invention discloses a clock tree synthesis method for a multi-macro unit multi-clock chip, comprising the following steps: S1. Manually inserting a plurality of buffers between each macro unit according to a certain range of connection distances between adjacent buffers, Build multiple H-type clock trees; S2. Replace all the buffers of the H-type clock tree with inverter pairs; S3. Divide the importance levels of all clocks on the chip; S4. Follow the order of the importance of the clocks from high to low , do RC balanced clock tree for each clock in turn. This method is suitable for chips with a large number of macro units and clocks, has good clock skew and clock delay, and uses fewer devices and consumes less power.

Description

Technical field [0001] The invention relates to a method for clock tree synthesis in chip back-end design, in particular to a method for clock tree synthesis of a chip with a particularly large number of macro units and clocks. Background technique [0002] At present, the clock network structures studied at home and abroad mainly include H tree structure, X tree structure, binary tree structure, balanced tree structure, grid structure, fishbone structure, etc. [0003] Among them, the binary tree structure is a commonly used tree-like clock distribution, which can obtain good clock tree synthesis results in irregular circuit designs. If the output resistance of the cell library buffer device is not much different from the wiring resistance of the clock source, one buffer can be used to drive the entire clock network. [0004] However, for deep sub-micron and more advanced processes, the output resistance of the buffer is difficult to achieve the same resistance as the wiring resist...

AI Technical Summary

Problems solved by technology

This also means that the H-tree structure has wiring restrictions and inconsistent fan-out restrictions, and when it enters the nanoscale process, the line length problem of the H-tree will make the problem of wiring delay more and more obvious, making this kind of structure is often used in small clock tree designs

[0008] On the other hand, using the H-type clock tree synthesis method, there are a large number of registers in a large-scale chip, and the tool cannot handle the H-type clock tree synthesis of a large number of registers.

Moreover, theoretically speaking, if the registers are placed irregularly, the tool will not be able to make an H-shaped clock tree well. If you try it manually, the workload will be very heavy.

Images