DFI standard DDR3 controller based on FPGA

Abstract

The present invention discloses a DFI standard DDR3 controller based on an FPGA. The DFI standard DDR3 controller comprises an AXI interface module, an AXI controller, a periodic read module, a protocol controller and a signal interface module which are electrically connected successively. The AXI interface module is used for receiving a user logic sent by the FPGA and sending the user logic to the AXI controller, and also used for receiving DDR3 memory data forwarded by the AXI controller and sending the memory data to the FPGA; the AXI controller is used for transforming the user logic into data in the form of an AXI protocol, and sending the data in the form of the AXI protocol to the periodic read module, and also used for receiving the DDR3 memory data sent by the periodic read module and sending the DDR3 memory data to the AXI interface module; and the periodic read module is used for providing periodic data strobe data DQS for dynamic calibration of a DDR3 physical layer, and also used for sending the data in an AXI form to the protocol controller periodically, and sending the DDR3 memory data to the AXI controller periodically.

Description

technical field [0001] The invention relates to the technical field of chip design, in particular to an FPGA-based DFI standard DDR3 controller. Background technique [0002] With the development of semiconductor technology, memory technology has also been developed rapidly. Among them, DDR3 memory particles have become the mainstream of memory due to their advantages of large capacity, high speed, and stable operation. DDR3 memory particles have added many new technologies. For example: introduce a leap (FLY_BY) topology to improve signal integrity; provide write leveling (WriteLeveling) and read leveling (ReadLeveling) mechanisms to compensate for the difference between data, clock signals and strobe signals brought by the FLY_BY structure between skew; add the ZQ calibration pin to calibrate the on-chip termination resistor (ODT) and output driver. [0003] The DDR3 controller mainly completes the data reading and writing of DDR3 memory particles, including the DDR3 con...

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Problems solved by technology

[0004] In chip design, FPGA is usually used to verify the function and performance of ASIC prototype system. Xilinx’s Virtex-7 series field programmable gate array (FPGA) verification platform can do 20 million ASIC prototype verification, but the difference between the DDR3PHY and the controller The interface between them does not adopt the DFI standard, and the DDR3 controller implemented by the existing ASIC usually adopts the DFI standard. In order to verify the ASIC prototype system on the Virtex-7 series FPGA platform, a method that can be implemented on the XilinxVirtex-7 series FPGA platform is required. DFI (DDR Physical Layer Interface) standard DDR3 controller

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