Test structure and method for optical correction of cmos device ion implantation

Abstract

The invention provides testing structure and method for optical correction of ion implantation in a complementary metal oxide semiconductor (CMOS) device. The prototype of a CMOS device wafer structure is reserved; the effects, for example, the size, the shape, the pattern density and the surrounding environment, on an ion implantation layer due to the CMOS environment can be really simulated; meanwhile, the electrical properties of the ion implantation layer can be tested through various test pins to relatively intuitively validate the optimization effect of the optical correction on the ion implantation layer, namely the effects on the isolation capability of the ion implantation layer due to the optical correction are monitored; and the adverse effects on optical correction of the ion implantation layer due to the pattern density of the domain are avoided.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a test structure and method for ion implantation optical correction of CMOS devices. Background technique [0002] Complementary Metal Oxide Semiconductor (CMOS) is the foundation of modern semiconductor integrated circuit technology and constitutes the most basic unit of digital integrated circuits. CMOS is an organic combination of NMOS transistors and PMOS transistors to form a logic device. Its advantage is that only when the logic state transitions, a large current will be generated, and in a stable logic state, only a very small current passes through, so it can Significantly reduces the power consumption of logic circuits. [0003] In the CMOS manufacturing process, the ion implantation process plays an important role and has a decisive impact on the performance and reliability of the device. The main applications of ion implantation include CMOS well...

AI Technical Summary

Problems solved by technology

However, as the line width of the ion implantation region becomes smaller and smaller, the feature size (CD) of the ion-implanted mask pattern itself and the spacing between the patterns are continuously reduced, making the monitoring error of the critical dimension in the mask pattern It is getting bigger and bigger, which ultimately leads to the fact that this traditional method of online monitoring of optical correction effects cannot meet the requirements of smaller-sized CMOS device manufacturing.

Images