Cross-clock domain asynchronous data processing method and apparatus

Abstract

Embodiments of the invention provide a cross-clock domain asynchronous data processing method and apparatus. The cross-clock domain asynchronous data processing method comprises: generating a continuous read and write command in a first clock domain, wherein the continuous read and write command comprises start-stop address information and a read and write mode of continuous data; performing synchronization processing on the continuous read and write command of the first clock domain, and obtaining a continuous read and write command in a second clock domain; and by using an asynchronous FIFO queue and a memory of the second clock domain, reading and writing the continuous data, wherein a memory address, in the memory, of the continuous data is determined by the continuous read and write command of the second clock domain. The cross-clock domain asynchronous data processing method does not need each storing operation to wait for data signal conversion of an asynchronous clock domain for data of a long continuous address, thus improving the data processing efficiency.

Description

technical field [0001] The invention relates to the technical field of data processing, in particular to a cross-clock domain asynchronous data processing method and a cross-clock domain asynchronous data processing device. Background technique [0002] In a complex digital circuit system, the entire system is often composed of multiple units or multiple printed circuit boards, so in the logic design of Application Specific Integrated Circuit (ASIC) and Field-Programmable Gate Array (Field-Programmable Gate Array, FPGA) , often design the interaction of signals between two clock domains or multiple clock domains. [0003] Usually, when reading and writing an asynchronous memory across clock domains, the following process can be performed: for each received data signal, first sample the data signal to obtain the data signal of the first clock domain; The data signal in the first clock domain is synchronized to obtain the data signal in the second clock domain; then the synch...

AI Technical Summary

Problems solved by technology

In the process of reading and writing, because each storage operation needs to wait for the data signal conversion of the asynchronous clock domain, a large number of clock cycles are consumed, especially when reading and writing a large section of continuous address space in the asynchronous memory, the above processing method will lead to Reduced data processing efficiency

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