Digital to Analog Converter

Abstract

The digital-to-analog converter includes a first-stage SAR-type sub-digital-to-analog conversion circuit, a second-stage SAR-type sub-digital-to-analog conversion circuit, an error amplifier circuit, and a digital error correction circuit; the first-stage SAR-type sub-digital-to-analog conversion circuit is used for input The signal is subjected to 6-bit primary quantization processing to obtain and output the high 6-bit signal to the digital error correction circuit, and output the remaining residual signal to the error amplifier circuit; the error amplifier circuit is used to amplify the residual signal and convert the amplified The signal is sent to the second-stage digital-to-analog conversion circuit; the second-stage SAR-type sub-digital-to-analog conversion circuit is used to perform 7-bit sub-quantization processing on the amplified signal to obtain and output the lower 7-bit signal to the digital error Correction circuit; the second-stage SAR-type sub-digital-to-analog conversion circuit and the first-stage SAR-type sub-digital-to-analog conversion circuit use the same reference voltage; the digital error correction circuit is used to add the high 6-bit signal and the low 7-bit signal for misalignment , to get a 12-bit digital quantization signal. The invention has simple structure and can effectively save power consumption.

Description

technical field [0001] The invention relates to a digital-to-analog converter. Background technique [0002] The successive approximation digital-to-analog converter, also known as the SAR ADC, uses a binary method algorithm to sequentially compare the input signal with the reference level to obtain the digital quantization result of the input signal. This serial comparison method makes the SAR ADC have the advantage of low power consumption compared with other types of ADCs, such as parallel (ie flash) and pipeline (ie pipeline) ADCs. [0003] The serial quantization method of the SAR ADC also limits the quantization speed of this ADC. In modern communication, it is necessary to transmit a large amount of multimedia information such as pictures and videos, and the bandwidth is extended to the order of 10Mhz, and the precision is required to be above 10bit. The SAR ADC seems to be stretched for such precision and speed communication requirements. [0004] Such as figure 1...

AI Technical Summary

Problems solved by technology

The pipelined ADC combines the characteristics of parallel ADCs. It is fast and can reach a quantization bandwidth of hundreds of Mhz. However, due to the need for n high-performance operational amplifiers, the power consumption of the pipelined ADC is large, which cannot meet the needs of low-power handheld communication devices. consumption application requirements

[0005] The existing Pipelined-SAR ADC uses a low-precision SAR ADC to replace the internal comparator of the pipelined ADC, so that it has the advantages of both SAR and pipelined ADCs. However, due to the existence of non-overlapping clocks and sampling clocks in the system , multi-bit successive approximation clock and clearing and other controls, complex timing is one of the difficulties in the realization of this structure

Images