A dual-bus memory controller

Abstract

The present invention provides a dual-bus memory controller. The controller comprises a PLB bus bridge circuit, an AXI bus bridge circuit, a DFI bus arbitration circuit, and a memory controller kernel. The PLB bus bridge circuit receives an access request from a PLB bus, and converts the request into a DFI bus standard request; the AXI bus bridge circuit receives an access request from an AXI bus, and converts the request into a DFI bus standard request; and the DFI bus arbitration circuit receives the DFI bus standard requests output by the PLB bus bridge circuit and the AXI bus bridge circuit, and sends the DFI bus standard requests to the memory controller kernel MCP after arbitration logicalization. According to the present invention, bus bridge logics are respectively designed for two bus standards, i.e. an external access request is converted into an internal access request of a memory controller; at least one time of cost of bus protocol conversion is reduced, thereby obtaining higher memory access efficiency; and the logic of the memory controller kernel does not need to be modified.

Description

technical field [0001] The invention belongs to the technical field of computer chip design, in particular to a dual-bus memory controller. Background technique [0002] In modern computer systems, memory is already an essential CPU peripheral device, with extremely high external data transfer rate and advanced address / command and control bus topology. The memory controller is also widely used in the core chips of various electronic products. The memory controller is an important part of the computer system to control the memory and exchange data between the memory and the CPU through the memory controller. The memory controller determines the memory performance of a computer system. . [0003] The current mainstream memory controllers usually only support one standard bus interface, but in today’s high-speed information systems, IPs with different bus interfaces often need to access memory at the same time, especially IP cores with AMBA AXI bus and IP cores with PLB bus ...

AI Technical Summary

Problems solved by technology

Too many bus standard conversions will seriously reduce memory access efficiency and lead to bus congestion

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