Integrated circuit element and manufacturing method therefor

Abstract

The invention provides an integrated circuit element, and the element comprises a first substrate which comprises a first patterning metal layer; a second substrate which is stacked on the first substrate and comprises a semiconductor material layer, a first dielectric layer, a second patterning metal layer, and a second dielectric layer. The second patterning metal layer is located between the first dielectric layer and the second dielectric layer, and has an overlapped region with the first patterning metal layer. The element also comprises a conduction loop which is located in the overlapped region and at least passes through the second substrate, so as to electrically connect the second and first patterning metal layers; and an insulating layer which is located between the conduction loop and the semiconductor material layer.

Description

technical field [0001] The invention relates to integrated circuit element technology, and relates to a three-dimensional stacked integrated circuit element and a manufacturing method thereof. Background technique [0002] Due to the advantages of high performance, low energy consumption, low cost, small size, and heterogeneous integration of integrated circuits, three-dimensional stacked integrated circuits have great potential to become a new direction for the development of System on Chip (SoC) technology, while through-substrate ( Through-SubstrateVia (TSV for short) packaging technology plays a key role, which can overcome the limitations of integrated circuit process scaling and low dielectric value materials, and achieve low-cost and high-efficiency electrical interconnection between chips. [0003] However, in the wafer-to-wafer bonding technology, when using substrate through holes to bond the metal layers in the upper and lower wafers, it is necessary to use two ma...

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Problems solved by technology

[0003] However, in the wafer-to-wafer bonding technology, when using substrate through holes to bond the metal layers in the upper and lower wafers, it is necessary to use two masks to perform a second substrate through hole etching process, and then use the laterally defined metal wires To connect the two substrates through holes to achieve the purpose of connecting the metal layers in the upper and lower wafers, this method requires two different substrate through-hole masks, and relatively more process steps are required, resulting in an increase in manufacturing costs.

However, if only one TSV mask is used to define the TSVs on different wafers, because the TSVs on different wafers have different depths, in order to ensure that both TSVs can be successfully connected to the metal layer, the etching step has a certain depth The metal layer under the shallower TSV will be over-etched, thus damaging the metal layer under the shallower TSV

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