Array substrate, preparing method thereof, and display panel

Abstract

The embodiment of the invention provides an array substrate, a preparing method thereof, and a display panel and relates to the technical field of display. The light-proof area occupied by thin film transistors and grid lines in the array substrate can be reduced, and the aperture ratio of the array substrate can be increased. The array substrate comprises a substrate body, an isolating layer located on the substrate body, the thin film transistors and the grid lines, wherein the isolating layer comprises a main layer parallel to the substrate body and a plurality of protruding parts which are located on the main layer and parallel to the grid lines, a line of thin film transistors arranged in the direction of the grid lines and one grid line are arranged on at least one of the two opposite side faces, parallel to the grid lines, of each protruding part, and the side faces where the thin film transistors and the grid lines are located are oblique surfaces which are arranged upward relative to the main layer. The display panel comprises the array substrate.

Description

technical field [0001] The present invention relates to the field of display technology, in particular to an array substrate, a preparation method thereof, and a display panel. Background technique [0002] The array substrate is provided with thin film transistors (ThinFilm Transistor, TFT for short) as pixel switches, transparent pixel electrodes for display, gate lines for controlling TFT gates, and data lines for controlling TFT source electrodes. [0003] Take LTPSTFT (LTPS is the English abbreviation of "LowTemperaturePolySilicon" for Low Temperature Polysilicon", which is commonly used in array substrates with top gate structure at present, and LTPSTFT means that the semiconductor material used in the active layer of TFT is LTPS) as an example, as follows: figure 1 As shown, in the LTPSTFT structure, the pattern of the active layer is usually U-shaped, and the part where the gate line overlaps with the U-shaped pattern of the active layer is the gate of the TFT. A pa...

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Problems solved by technology

Since the electrical performance of the TFT when it is turned on is related to the part of the active layer corresponding to the part between the source and the drain, that is, the area of ​​the channel (channel) when the TFT is turned on, in the current LTPSTFT structure, The gate lines need to have a certain width, and the U-shaped pattern of the active layer also needs to have a certain U-shaped length, so that the gate lines and TFTs occupy a large area of ​​the array substrate

[0004] In addition, when the gate in the TFT is directly connected to the gate line, limited by the current manufacturing process, the width of the gate line is also difficult to make very narrow, resulting in the gap occupied by the gate line and TFT in the current array substrate. The light-transmitting area is usually large, which restricts the further improvement of the aperture ratio of the array substrate

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