Formation method of semiconductor structure
A semiconductor and isolation structure technology, which is applied in the field of semiconductor structure formation, can solve the problems of poor performance and poor performance of semiconductor structures, and achieve the effect of improving performance and improving uniformity
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Embodiment 1
[0069] reference Figure 5 , A semiconductor substrate 300 is provided, and at least one isolation structure is formed on the semiconductor substrate 300.
[0070] In this embodiment, the semiconductor substrate 300 is a silicon substrate. In other embodiments, the semiconductor substrate may also be silicon-on-insulator. The isolation structure is a shallow trench isolation structure (STI). In other embodiments, the isolation structure may also be other isolation structures known to those skilled in the art, for example, a field oxide layer isolation structure.
[0071] In this embodiment, the method of forming the shallow trench isolation structure is: forming at least one opening (not shown) on the semiconductor substrate 300, and depositing an isolation layer in the opening. In this embodiment, the material of the isolation layer is silicon oxide. The silicon oxide fills the opening and covers the semiconductor substrate 300. Next, the silicon oxide layer higher than the se...
Embodiment 2
[0117] The difference between the second embodiment and the first embodiment is that the semiconductor substrate is not divided into an NMOS region and a PMOS region, and the corresponding isolation structure, the first groove and the first semiconductor material layer in the first groove are also not divided into the NMOS region. And PMOS area. The method for forming the semiconductor structure in this embodiment is specifically as follows:
[0118] Provide semiconductor substrate;
[0119] Forming at least one isolation structure on the semiconductor substrate;
[0120] Forming a first groove in the semiconductor substrate on both sides of the isolation structure, the depth of the first groove is smaller than the depth of the isolation structure;
[0121] Filling the first groove with a first semiconductor material layer and the first semiconductor material layer is higher than the semiconductor substrate, and the first semiconductor material layer higher than the semiconductor sub...
Embodiment 3
[0127] As the size of semiconductors is further reduced, active regions made of elements of Group III and Five are introduced into NMOS transistors to replace active regions made of germanium. The difference between the third embodiment and the first embodiment is that the size of the semiconductor structure formed by the method of the third embodiment is smaller than the size of the semiconductor structure formed by the method of the first embodiment. In this embodiment, the method for forming a semiconductor device containing an NMOS transistor whose source region is a group III or group element is as follows:
[0128] First, refer to the Figure 5 ~ Figure 9 and Figure 5 ~ Figure 9 Detailed description of each step involved in.
[0129] What needs to be added is the reference Image 6 In this embodiment, the depth of the first groove 303 in the NMOS region is greater than or equal to 400 angstroms and less than or equal to 600 angstroms, and the reason why the depth of the firs...
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