FinFET structure and manufacture method thereof

A manufacturing method and device manufacturing method technology, applied in semiconductor/solid-state device manufacturing, semiconductor devices, electrical components, etc., to achieve the effects of making source-drain contacts conveniently, low subthreshold slope and leakage current, and improving device performance

Active Publication Date: 2016-04-06
INST OF MICROELECTRONICS CHINESE ACAD OF SCI
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] The invention provides a U-shaped FinFET structure and a manufacturing method thereof, and proposes a new device structure on the basis of the existing FinFET tech

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  • FinFET structure and manufacture method thereof
  • FinFET structure and manufacture method thereof
  • FinFET structure and manufacture method thereof

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Embodiment Construction

[0036] In order to make the object, technical solution and advantages of the present invention clearer, the embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0037] Embodiments of the present invention are described in detail below, examples of which are shown in the drawings, wherein the same or similar reference numerals designate the same or similar elements or elements having the same or similar functions throughout. The embodiments described below by referring to the figures are exemplary only for explaining the present invention and should not be construed as limiting the present invention.

[0038] The present invention provides a FinFET structure, comprising: a substrate; a first fin and a second fin, the first and second fins are located above the substrate and parallel to each other; a gate stack, the a gate stack covering the substrate and part of the sidewalls of the first and second fins; a source...

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Abstract

The invention provides a FinFET structure and a manufacture method thereof. The FinFET structure comprises a substrate, a first fin, a second fin, a grid lamination layer, a source region, a drain region, sidewalls and a substrate channel region, wherein the first and second fins parallel with each other are placed on the substrate; the grid lamination layer covers the substrate and part of the sidewalls of the first and second fins; the source region is placed in the area, not covered by the grid lamination layer, of the first fin; the drain region, is placed in the area, not covered by the grid lamination layer, of the second fin; the sidewalls are placed at the two sides of the first fin and the two sides of the second fin respectively and on the grid lamination layer to isolate the source region, the drain region and the grid lamination layer from one another; and the substrate channel region is placed in the substrate in an area close to the upper surface. According to the invention, the new device structure is provided on the basis of a present FinFET technology, and the grid length of the device is not limited by the footprint size, and the problem caused by the short channel effects is effectively solved.

Description

technical field [0001] The present invention relates to a method for manufacturing a semiconductor device, in particular to a method for manufacturing a FinFET. technical background [0002] Moore's Law states that the number of transistors that can be accommodated on an integrated circuit doubles every 18 months, and the performance also doubles at the same time. At present, with the development of integrated circuit technology and technology, devices such as diodes, MOSFETs, and FinFETs have appeared successively, and the size of nodes has been continuously reduced. However, since 2011, silicon transistors have approached the atomic level and reached the physical limit. Due to the natural properties of this material, in addition to the short-channel effect, the quantum effect of the device also has a great impact on the performance of the device. The speed and performance of silicon transistors are hard to break through. Therefore, how to greatly improve the performance ...

Claims

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Application Information

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IPC IPC(8): H01L27/088H01L29/78H01L21/8234H01L21/336
CPCH01L29/78
Inventor 尹海洲刘云飞李睿
Owner INST OF MICROELECTRONICS CHINESE ACAD OF SCI
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