Analog decoding circuit design method and system

Abstract

The invention provides a design method and system for a simulation decoding circuit. The method includes the steps that S1, a factor graph model is set up according to a preset check matrix, and the corresponding simulation decoding circuit is set up according to the factor graph model; S2, input parameters of a sum-product model circuit are designed according to preset circuit design requirements and corresponding formulas; S3, related mismatch parameters and related delay parameters of the sum-product model circuit are obtained; S4, according to the related mismatch parameters and the related delay parameters, the calculation process, considering the mismatch effect and circuit dynamic behavior influence factors, of a simulation decoding circuit model is conducted to obtain a BER performance simulation result; S5, whether the simulation result meets a preset requirement or not is judged, if yes, the flow path is finished, otherwise, the input parameters in the step S2 are modified, and simulation continues to be conducted until the simulation result meets the preset requirement. Input parameter design and system level characteristics can be related in the design method, and optimized guide can be provided for circuit design.

Description

technical field [0001] The invention relates to the technical field of communication signal processing, in particular to an analog decoding circuit design method and system. Background technique [0002] In 1998, Loeliger and Hagenauer respectively proposed the use of classical analog electronic networks for error correction code decoding, and first proposed the concept of "analog decoding". At present, different research teams have implemented analog decoding chips of different code types, as shown in Table 1. The test results of the chip show that, compared with the digital implementation, when implementing the same iterative decoding algorithm (sum product algorithm or minimum sum algorithm), if the decoding rate is the same, the power consumption of the analog decoding circuit is lower; In the case of the same code power consumption, the speed of the analog decoding circuit is higher. [0003] Table 1 Performance comparison of analog iterative decoding chips [0004] ...

AI Technical Summary

Problems solved by technology

However, for analog decoding circuits with high-complexity error correction patterns, SPICE-level circuit model simulation is impractical

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