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Bit line lead-out circuit in memory array and memory

A memory array and mid-bit line technology, applied in the field of memory, can solve problems such as insufficient memory array bit line wiring channels, performance degradation of storage devices, and all bit line connections, etc., to solve the problem of insufficient bit line wiring channels, increase area, and improve Effects on memory performance

Inactive Publication Date: 2016-04-20
GIGADEVICE SEMICON (BEIJING) INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

For a highly integrated memory chip, if you want to connect all the bit lines in the memory chip to the decoding circuit, it will take up a very large layout area of ​​the memory chip, reduce the area of ​​the decoding circuit of the memory chip, and cause sacrifices. The transistor size of the decoding circuit is exchanged for the wiring space of the bit lines; if the wiring space of the bit lines is reduced, although the area of ​​the decoding circuit may be increased, it is not enough to connect all the bit lines to the decoding circuit, resulting in a decrease in the performance of the memory device
It can be seen that there is a problem of insufficient bit line wiring channels of the memory array in the prior art

Method used

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  • Bit line lead-out circuit in memory array and memory
  • Bit line lead-out circuit in memory array and memory
  • Bit line lead-out circuit in memory array and memory

Examples

Experimental program
Comparison scheme
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Embodiment 1

[0028] refer to figure 1 , is a flow chart of a bit line lead-out circuit in a memory array provided by Embodiment 1 of the present invention. The technical solution of this embodiment is applicable to situations where the memory chip wiring channels are insufficient or the layout area is saved. The memory can be any memory chip including bit lines and word lines, such as NOR flash memory, NAND flash memory and the like. In order to describe the bit line lead-out circuit in the memory array provided by Embodiment 1 of the present invention in more detail, here, the attached Figure 2-4 Give a detailed explanation.

[0029] A bit line lead-out circuit in a memory array provided by the present invention includes:

[0030] Step 110, dividing the bit lines in the memory array into first type bit lines and second type bit lines;

[0031] Step 120, the first type of bit line is led out through the first direction, and connected to the first decoding circuit;

[0032] Step 130, t...

Embodiment 2

[0051] refer to Figure 5 , is a schematic diagram of the memory provided by Embodiment 2 of the present invention. A memory provided by the present invention, the memory includes a decoding circuit, a global bit line 240 and a memory array 210, wherein the decoding circuit includes a first decoding circuit 220 and a second decoding circuit 230, and the memory Array 210 includes an array of word lines and an array of bit lines;

[0052] The word lines in the word line array are perpendicular to the bit lines in the bit line array;

[0053] The bit line lead-out circuit of the bit line array is the circuit described in the first embodiment above;

[0054] The first decoding circuit 220 is respectively connected to the bit line array in the memory array 210 and the global bit line 240;

[0055] The second decoding circuit 230 is respectively connected to the bit line array in the memory array 210 and the global bit line 240 .

[0056] As mentioned above, the structure of the...

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PUM

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Abstract

The invention discloses a bit line lead-out circuit in a memory array and a memory. In the circuit, bit lines in the memory array are divided into first-type bit lines and second-type bit lines. The first-type bit lines are lead-out in a first direction and are connected to a first decoding unit. The second-type bit lines are lead-out in a first direction and are connected to a second decoding unit. In the invention, the bit lines in the memory array are divided into the first-type bit lines and the second-type bit lines, wherein the first-type bit lines are lead-out in the first direction and are connected to the first decoding unit and the second-type bit lines are lead-out in the first direction and are connected to the second decoding unit, so that the bit lines are loosen in arrangement and only occupy a small domain area in the memory, and correspondingly, the area of the decoding circuit is increased. Meanwhile, within limited wiring pathways, all the bit lines can be connected to the decoding circuit, so that a problem of insufficient wiring pathways of the bit lines is solved. The lead-out circuit saves domain area and increases the area of the decoding circuit and further improves the performance of the memory.

Description

technical field [0001] The invention relates to the field of memory technology, in particular to a bit line lead-out circuit in a memory array and a memory. Background technique [0002] The layout design of a traditional memory chip includes bit lines, word lines, decoding circuits, and memory cells. Several storage cells in the memory are used for programming / erasing programs, instructions and other data. Memory cells on multiple bit lines are also often arranged in blocks or arrays. The decoding circuit is usually connected with the array of memory cells, specifically, the word line and the bit line, and is used to select the memory cell through the corresponding word line and the bit line, so as to operate the memory cell, so each memory cell in the memory is can be selected by the appropriate combination of wordlines and bitlines. [0003] In the prior art, in the layout design of the memory chip, several bit lines connected to multiple memory cells are drawn from on...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G11C7/18
Inventor 舒清明胡洪张建军
Owner GIGADEVICE SEMICON (BEIJING) INC