Array substrate and fabrication method thereof and display panel

Abstract

The invention discloses an array substrate and a fabrication method thereof and a display panel. The array substrate comprises a substrate, a polysilicon channel layer, a gate insulating layer, a gate, a first interlayer insulation layer, a second interlayer insulation layer, a source and a drain, wherein the polysilicon channel layer, the gate insulating layer, the gate, the first interlayer insulation layer, the second interlayer insulation layer, the source and the drain are sequentially stacked on the substrate; the source and the drain are arranged on the second interlayer insulation layer; and one side, far away from the substrate, of the first interlayer insulation layer and one side, far away from the substrate, of the gate are located on the same plane, so that one side, far away from the substrate, of the second interlayer insulation layer is a plane; one side far away from the substrate, of the source is the plane; and one side, far away from the substrate, of the drain is also the plane. In the manner, parasitic capacitance can be reduced; and the stability of electric signal transmission is ensured.

Description

technical field [0001] The present application relates to the field of display technology, in particular to an array substrate, a manufacturing method thereof, and a display panel. Background technique [0002] At present, the low temperature polysilicon technology (English: Low Temperature Poly-silicon, LTPS for short) type is the mainstream of the liquid crystal display panel. Such as figure 1 As shown, the LTPS liquid crystal display panel needs to stack a polysilicon (English: poly) channel layer 11, a gate 12, an interlayer insulating layer 15 for insulating the gate 12 from the source 13 and the drain 14 on the substrate, and then The source electrode 13 and the drain electrode 14 are provided on the inter insulating layer 15 . [0003] Since the polysilicon channel layer 11 and the gate electrode 12 have a certain film thickness, the surface where the inter-insulation layer is located is uneven, and the film formation of the existing inter-insulation layer usually a...

AI Technical Summary

Problems solved by technology

[0003] Since the polysilicon channel layer 11 and the gate electrode 12 have a certain film thickness, the surface where the inter-insulation layer is located is uneven, and the film formation of the existing inter-insulation layer usually adopts chemical vapor deposition (English: Chemical Vapor Deposition, abbreviated: CVD) A film with a certain thickness is made, so the top layer of the inter-insulating layer is also uneven, which in turn causes the source and drain electrodes disposed on the inter-insulating layer to be uneven

The uneven structure of the source and drain will affect its electrical properties and generate more parasitic capacitance, resulting in unstable electrical signal transmission and affecting device performance

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