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A GPU 3D Engine On-Chip Storage Hierarchy for Unified Dyeing Architecture

A storage hierarchy and storage structure technology, applied in processor architecture/configuration, details related to image processing hardware, image memory management, etc., can solve complex storage hierarchy design, high throughput of vertex and pixel coloring tasks, and Solve problems such as high utilization of array resources, achieve the effect of improving memory data bandwidth utilization, improving data bandwidth utilization, and improving access speed

Active Publication Date: 2018-12-25
XIAN AVIATION COMPUTING TECH RES INST OF AVIATION IND CORP OF CHINA
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AI Technical Summary

Problems solved by technology

In the GPU of the unified coloring architecture, the resource utilization rate of the unified coloring array is high, and the throughput of vertex and pixel coloring tasks is large. High-performance on-chip storage hierarchy design is more important and more complex

Method used

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  • A GPU 3D Engine On-Chip Storage Hierarchy for Unified Dyeing Architecture
  • A GPU 3D Engine On-Chip Storage Hierarchy for Unified Dyeing Architecture

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Embodiment Construction

[0027] The technical solutions of the present invention are clearly and completely described below in conjunction with the accompanying drawings and specific embodiments. Obviously, the described embodiments are only a part of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without making creative work are all Belong to the protection scope of the present invention.

[0028] see figure 1 , The structure of the present invention includes a four-layer storage structure, which are respectively: a register layer, an on-chip SRAM&L1Cache layer, an L2Cache layer, and a display memory layer. The register layer is connected to the on-chip SRAM layer, the on-chip SRAM layer & L1Cache layer is connected to the L2Cache layer or the display memory layer, and the L2Cache is connected to the display memory layer. The register layer can directly perform data read and wri...

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Abstract

The present invention relates to a GPU3D engine on-chip memory hierarchy structure facing unified dyeing architecture. The structure comprises four layers of storage structures which are a register layer, an on-chip SRAM&L1Cache layer, an L2Cache layer and a display memory layer from top to bottom. The register layer is connected to the on-chip SRAM&L1Cache layer which is connected to the L2Cache layer or the display memory layer. The L2Cache layer is connected to the display memory layer. The data access delay in the graphics processing process can be effectively reduced, and the data bandwidth utilization rate of a display memory is improved.

Description

technical field [0001] The invention relates to the technical field of computer hardware, in particular to an on-chip storage hierarchy of a GPU 3D engine oriented to a unified dyeing architecture. Background technique [0002] With the continuous increase of graphics applications, the early solution of graphics rendering by CPU alone has been difficult to meet the graphics processing needs of performance and technology growth, and the graphics processing unit (Graphic Processing Unit, GPU) came into being. Since the release of the first GPU product by Nvidia in 1999, the development of GPU technology has mainly gone through the fixed-function pipeline stage, the stage of separate dyeing processor architecture, and the stage of unified dyeing processor architecture. The graphics drawing of the computer has been gradually extended to the field of general computing. The high-speed, parallel features and flexible programmability of the GPU pipeline provide a good operating pla...

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06T1/60G06T1/20
CPCG06T1/20G06T1/60G06T2200/28
Inventor 张骏田泽韩立敏郑新建任向隆吴晓成
Owner XIAN AVIATION COMPUTING TECH RES INST OF AVIATION IND CORP OF CHINA
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