Array substrate, manufacturing method thereof, and display device

Abstract

The invention provides an array substrate, a fabrication method thereof and a display device, belonging to the technical field of display. The fabrication method of the array substrate comprises the following steps of forming a first conductive pattern on the substrate; forming an insulation layer comprising via holes on the substrate provided with the first conductive pattern, wherein at least one part of the first conductive pattern is exposed out of the via holes; immersing the substrate provided with the insulation layer in a metal salt solution; and inputting an electric signal to the first conductive pattern so as to make metal ions in the metal salt solution reduced and deposited in the via holes to form a conductive connection part after the metal salt solution in the via holes is in contact with the first conductive pattern. With the technical scheme provided by the invention, the electrical connection status of the array substrate in the via holes can be optimized, and the production yield of the array substrate is improved.

Description

technical field [0001] The present invention relates to the field of display technology, in particular to an array substrate, a manufacturing method thereof, and a display device. Background technique [0002] With the development of display technology, the PPI (pixel density) of the display panel is gradually increasing, the size of TFT (thin film transistor) is getting smaller and smaller, and the corresponding Via hole (via hole) size is also getting smaller. [0003] In the manufacturing process of the existing array substrate, PVD (Physical Vapor Deposition, Physical Vapor Deposition) method is usually used to deposit a conductive layer at the via hole of the insulating layer, so as to realize the connection between the conductive layer and the conductive pattern under the insulating layer. This method requires that the size of the via hole should not be too small. If the size of the via hole is too small, poor contact will easily occur between the conductive layer and ...

AI Technical Summary

Problems solved by technology

[0003] In the manufacturing process of the existing array substrate, PVD (Physical Vapor Deposition, Physical Vapor Deposition) method is usually used to deposit a conductive layer at the via hole of the insulating layer, so as to realize the connection between the conductive layer and the conductive pattern under the insulating layer. This method requires that the size of the via hole should not be too small. If the size of the via hole is too small, poor contact will easily occur between the conductive layer and the conductive pattern formed at the via hole, resulting in a decrease in the production yield of the array substrate.

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