Equal gate height control method for semiconductor devices with different pattern densities
A pattern density, semiconductor technology, applied in semiconductor/solid-state device manufacturing, semiconductor devices, electric solid-state devices, etc., can solve problems such as adverse effects, uneven polysilicon layer IC manufacturing process, etc.
Active Publication Date: 2018-10-23
TAIWAN SEMICON MFG CO LTD
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Problems solved by technology
Inhomogeneity of the polysilicon layer or its topology can adversely affect the IC manufacturing process
Method used
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[0028] It should be understood that the following disclosure provides a variety of different embodiments or examples for implementing different features of the present invention. Specific examples of components and arrangements will be described below to simplify the invention. Of course, these are only examples and are not intended to limit the invention. In addition, the present invention may repeat reference symbols and / or characters in multiple instances. This repetition is used for the purpose of simplification and clarity, and does not itself represent the relationship between the multiple embodiments and / or configurations. In addition, in the following invention, a component formed on, connected to, and / or coupled to another component may include an embodiment in which the component is formed by direct contact, and may also include an embodiment in which an additional component may be formed between the components so that the component is not Example of direct contact....
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A method of forming a semiconductor integrated circuit (IC) having substantially equal gate heights regardless of having different pattern densities in different regions of the IC, the method comprising: providing in a first region of the IC A substrate having a first pattern density in the IC and a second pattern density in the second region of the IC; forming a first polysilicon layer over the substrate, the first polysilicon layer having a non-uniform upper surface; forming a stop layer over the first polysilicon layer, treating the stop layer to change its etch selectivity relative to the first polysilicon layer; forming a second polysilicon layer over the stop layer; removing the second polysilicon layer On top of the silicon layer, the stop layer and the first polysilicon layer, the remainder of the first polysilicon layer has a planar upper surface. The present invention relates to an equal gate height control method for semiconductor devices with different pattern densities.
Description
Technical field [0001] The present invention relates to an equal gate height control method for semiconductor devices with different pattern densities. Background technique [0002] The semiconductor integrated circuit (IC) industry has experienced rapid development. In the course of this development, the functional density of the device is generally increased, while the size or geometric size of the device components is reduced. This scaling down process generally provides benefits by increasing production efficiency, reducing costs, and / or improving performance. This scaling down process also increases the complexity of processing and manufacturing ICs, and in order to achieve these advancements, similar developments in IC manufacturing are required. [0003] Semiconductor ICs include devices such as transistors, capacitors, resistors, and inductors formed in or on the substrate of the IC using photolithography and patterning techniques. Depending on the design of the IC, thes...
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IPC IPC(8): H01L21/8234
CPCH01L21/823431H01L21/823437H01L21/31053H01L21/845H01L27/1211H01L29/66H01L29/4916H01L29/66568H01L29/6675H01L21/28035H01L21/31116H01L21/31144H01L21/3115H01L21/3212H01L21/823481H01L29/66545
Inventor 林毓超黄明杰陈昭成
Owner TAIWAN SEMICON MFG CO LTD