Switched mode power amplifier with ideal iq combining
A technology for power amplifiers and converters, applied in power amplifiers, amplifiers with semiconductor devices/discharge tubes, amplifiers, etc., can solve problems such as insufficient PA stabilization time and data corruption
Pending Publication Date: 2016-05-11
TEXAS INSTR INC
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Problems solved by technology
[0011] The first problem is that the implementation requires the use of multi-stage PAs, even if I and Q are implemented independently using a single stage
The second problem is that I to Q leakage manifests as data corruption
The leakage is due to insufficient PA settling time available for potentially large data magnitude excursions, which can be as large as going from zero to (I+Q )
Method used
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Embodiment Construction
[0025] A first aspect of the invention is directed to providing a converter to convert an IQ signal into an I magnitude, an I sign, a Q magnitude and a Q sign.
[0026] A second aspect of the invention is directed to setting the LO to provide a clock with a period T, setting the I pulse generator and the Q pulse generator to generate four pulses of a particular duty cycle of the LO clock (the start times of the pulses being T / 4 apart ) and setting an I-phase selector and a Q-phase selector to provide a strobe pulse based on the pulse generator output and the I-sign and Q-sign.
[0027] A third aspect of the invention is directed to arranging Boolean logic gates to gate the IQ amplitude data into the four T / 4 slots making up the LO cycle based on the phase selector output and to combine the amplitude data into a single bit stream.
[0028] A fourth aspect of the present invention is directed to setting a high efficiency CMOS switching mode PA to amplify a single bit stream and ...
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The invention relates to a switched mode power amplifier with an ideal IQ combining. An I converter (502) outputs I sign data and I magnitude data based on received I data. A Q converter (504) outputs Q sign data and Q magnitude data based on received Q data. An I clock (406) generates an I phase based ort the I sign data. A Q clock generates a Q phase based on the Q sign data. An I modulator (514) generates an I magnitude pulse stream based on the I magnitude data. A Q modulator (516) generates a Q magnitude pulse stream based on the Q magnitude data. A digital logic component (518) generates an output signal based on the I phase, the I magnitude pulse stream, the Q phase and the Q magnitude pulse stream. A power amplifier (526) generates an amplified signal based on the output signal.
Description
technical field [0001] The present invention relates generally to power amplifiers, and more particularly to wireless transmitter structures with switched mode power amplifiers. Background technique [0002] Due to the development of wireless devices, wireless applications have rapidly grown into an important market. The development of low-cost complementary metal-oxide-semiconductor (CMOS) technology has made it a natural choice for radio frequency (RF) transceivers in wireless applications. Its progress has made it possible to integrate baseband and other functional blocks. CMOS technology will be the most viable solution for full integration on a single die reducing package form factor and its cost. In addition, due to its mature process technology and high integration, CMOS technology provides good thermal characteristics and low cost advantages. In power amplifiers (PAs), performance issues are output power, efficiency, linearity, yield, and reliability. In constant...
Claims
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IPC IPC(8): H03F3/24H03C3/40H03C5/00
CPCH03C3/40H03C5/00H03F3/24H03F2200/336H03F2200/331H03F2200/324H03F1/0227H03F3/245H03F3/217H03F3/19H04L27/3405H03F2200/451
Inventor 吉里什·拉金德郎拉凯什·库马尔阿洛克·普拉卡什·乔希苏巴希什·幕克吉克里希纳斯瓦米·程加拉吉安阿普·西瓦达斯
Owner TEXAS INSTR INC