A device and method for preventing bus deadlock
A bus and deadlock technology, which is applied in the direction of instrumentation, electrical digital data processing, etc., can solve problems such as bus deadlock, and achieve the effect of preventing bus deadlock
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Embodiment 1
[0043] In order to solve the technical problem of bus deadlock, this embodiment provides a device for preventing bus deadlock, which is applied to a system that performs data interaction with the processor and peripherals through the bus, such as figure 1 As shown, the device in this embodiment includes: a peripheral delay unit 101, a processor delay unit 102, and a state monitoring unit 103; wherein, the peripheral delay unit 101 is arranged between the bus and the peripherals, and the processor delay unit 102 is set between the processor and the bus;
[0044] The peripheral hardware delay unit 101 is used to monitor the bus status between the bus and the peripheral hardware, obtain the first bus status signal and send it to the status monitoring unit 103, and adjust the first bus status between the bus and the peripheral hardware according to the reset control command received. A handshake signal for reset operation;
[0045]Usually, the bus includes common on-chip buses, s...
Embodiment 2
[0074] This embodiment is based on the method for preventing chip bus deadlock implemented by the device described in Embodiment 1, such as image 3 As shown, the method for preventing chip bus deadlock described in this embodiment includes:
[0075] S201: Monitor the bus state between the bus and the peripheral, and obtain a first bus state signal;
[0076] This step can be completed by the peripheral delay unit 101 arranged between the bus and the peripheral; the first bus status signal includes the transmission status of all signals in the bus.
[0077] S202: Monitor the bus state between the bus and the processor to obtain a second bus state signal;
[0078] This step can be completed by the processor delay unit 102 arranged between the bus and the processor; the second bus status signal includes the transmission status of all signals in the bus.
[0079] In practical applications, the execution order of step S201 and step S202 is not limited.
[0080] S203: Timing the ...
Embodiment 3
[0101] This embodiment describes the present invention in detail through an actual scene. The processing of this embodiment includes:
[0102] S301: Monitor the bus state between the bus and the peripheral, and obtain a first bus state signal;
[0103] The first bus state monitoring module of the peripheral delay unit monitors the first bus state signal between the bus and the peripheral, and sends the first bus state signal to the state monitoring unit.
[0104] This step can be completed by the peripheral delay unit 101 arranged between the bus and the peripheral; the first bus status signal includes the transmission status of all signals in the bus.
[0105] Wherein, the peripheral device delay unit 101 is used to control the first handshake signal of the bus connected to the peripheral device. The number of peripheral delay units 101 is set according to the number of peripherals. Generally, each peripheral chip needs to be provided with a peripheral delay unit, or a peri...
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