Low-delay airborne gigabit Ethernet switching configuration
A Gigabit Ethernet, low-latency technology, applied in the design improvement field of high-speed, low-latency Ethernet switching architecture, can solve problems such as large discreteness, impact of clock synchronization accuracy, data frame transmission delay, etc., and achieve low development costs and production cost effects
Inactive Publication Date: 2016-06-01
CHINESE FLIGHT TEST ESTAB
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In addition, for the support of the precision clock synchronization protocol IEEE1588, since the general switch needs to meet the dynamic changes of each network port, the design of its switching structure and scheduling mechanism usually leads to delays in data frame transmission and large discreteness, so that clock synchronization Accuracy has a big impact
[0003] Due to the high requirements for the clock synchronization of each data acquisition node in the airborne test system, it is difficult to implement the performance index requirements of the airborne network test using the traditional general-purpose switching architecture
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[0017] The switching architecture can be implemented by using a general-purpose FPGA device with a certain capacity and corresponding peripheral circuits. The specific implementation method includes the following main contents:
[0018] Core switching circuit: The core switching circuit of the switching architecture is implemented by multiple data selectors, and each data selector is generated by logic resources inside the FPGA. The switching circuit is required to support the transmission rate of 10M / 100M / 1000M Ethernet, so its internal switching rate should meet the highest transmission rate requirement. Select the current new series of FPGA devices, whose performance index can well meet the index requirements of the switching circuit.
[0019] Taking XilinxVirtex6 as an example, each SLICE in this device contains two 6-input LUT units, and each LUT can be configured as a 4-to-1 data selector. Therefore, in this structure, connecting 5 LUTs in series can realize A 1-bit 16-...
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The invention provides a low-delay airborne gigabit Ethernet switching configuration which is characterized in that the low-delay airborne gigabit Ethernet switching configuration comprises a controller circuit, a core switching circuit and a peripheral circuit connected with the controller circuit and the core switching circuit, the controller circuit and the core switching circuit are realized by the same core FPGA device, the peripheral circuit comprises network ports, a physical layer chip and an MAC layer cache circuit which are connected in sequence, and the MAC layer cache circuit is realized by a plurality of peripheral FPGA devices according to the number of the ports.
Description
technical field [0001] The invention belongs to the computer network communication technology, and relates to the design improvement of the high-speed, low-delay Ethernet exchange framework. Background technique [0002] In the airborne test system using Ethernet for data transmission, each data node has the characteristics of relatively fixed transmission route and stable data transmission rate, which has high requirements on the transmission delay and stability of the transmission network. In addition, for the support of the precision clock synchronization protocol IEEE1588, since the general switch needs to meet the dynamic changes of each network port, the design of its switching structure and scheduling mechanism usually leads to delays in data frame transmission and large discreteness, so that clock synchronization Accuracy has a big impact. [0003] Because the clock synchronization requirements of each data acquisition node in the airborne test system are relatively...
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IPC IPC(8): H04L12/931
Inventor 单文军郭平凡杨廷梧何晓文周雪纯
Owner CHINESE FLIGHT TEST ESTAB