Hybrid analog-to-digital converter using digital slope analog-to-digital converter and related hybrid analog-to-digital conversion method thereof
A technology of digital converter and digital conversion, which is applied in the field of hybrid analog-digital converter and hybrid analog-digital conversion, and can solve the problems of high power consumption, increased design complexity of gain calibration, and halving the maximum conversion rate, etc.
Active Publication Date: 2016-06-29
MEDIATEK INC
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Problems solved by technology
Regarding the traditional noise-tolerant SARADC, it reduces the comparator power in the first bit period by using a coarse comparator, but the fine comparator will still be in the next bit period Consume a lot of power to achieve a signal-to-noise ratio of over 60dB
Regarding the traditional SAR-assisted pipelined (SAR-assisted pipelined) ADC, it does not require a low-noise comparator, but it will introduce an inter-stage gain error (gainerror)
While gain calibration adds complexity to the design
Additionally, the amplifier and subsequent stages will introduce additional noise and area to the ADC
Regarding the traditional fully-differential digital slope (fully-differential digital slope) ADC, it has inherently low noise due to quantizing the signal in the time domain, but its hardware and resolution increase exponentially, and its maximum conversion rate increases with each increase of 1 bit resolution will be halved
Therefore, this conventional fully differential digital ramp ADC is not attractive for resolutions higher than 8 bits
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[0015] Certain terms are used throughout the specification and following claims to refer to particular components. Those skilled in the art should understand that hardware manufacturers may use different names to refer to the same component. This document does not use the difference in name as a way to distinguish components, but uses the difference in function of components as a criterion for distinguishing. In the following description and claims, the terms "comprising" and "comprising" are open-ended terms, so they should be interpreted as "including but not limited to". In addition, the term "coupled" herein includes direct and indirect electrical connection means. Therefore, if a device is coupled to another device, it means that the one device may be directly electrically connected to the other device, or indirectly electrically connected to the other device through other devices or connecting means.
[0016] The main idea of the invention is to combine different ADC...
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A hybrid analog-to-digital converter (ADC) includes a plurality of analog-to-digital conversion circuits and a combining circuit. The analog-to-digital conversion circuits generate a plurality of partial digital outputs for a same analog input, respectively, wherein the analog-to-digital conversion circuits include a digital slope ADC used to perform signal quantization in a time domain. The combining circuit combines the partial digital outputs generated from the analog-to-digital conversion circuits to generate a final digital output of the analog input.
Description
[0001] This application claims the priority of U.S. Provisional Patent Application No. 62 / 042,886 filed on August 28, 2014, the entire contents of which are included in the present invention. 【Technical field】 [0002] The disclosed embodiments of the present invention relate to converting an analog input to a digital output, and more particularly, to a hybrid analog-to-digital converter using a digital ramp analog-to-digital converter and a corresponding hybrid analog-to-digital conversion method. 【Background technique】 [0003] The successive approximation register (Successive Approximation Register, SAR) analog-to-digital converter (Analog to Digital Converter, ADC) is an analog-to-digital converter that converts a continuous analog waveform into a discrete representation through a search scheme. One of the most common types of SARADC, the switched-capacitor (or charge redistribution) SARADC, uses a switched-capacitor network of multiple capacitors. The plurality of capac...
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IPC IPC(8): H03M1/38H03M1/56
CPCH03M1/145H03M1/468H03M1/54H03M1/38
Inventor 刘纯成
Owner MEDIATEK INC