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Redundancy metal filling region layout processing method and system

A technology for filling areas and redundant metals, applied in electrical digital data processing, special data processing applications, instruments, etc., can solve problems such as inconvenient intelligent filling of redundant metals, missing processing results, etc.

Active Publication Date: 2016-07-06
INST OF MICROELECTRONICS CHINESE ACAD OF SCI
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0006] The present invention provides a method and system for processing the layout of redundant metal filled regions, which solves the problems of missing defects existing in the layout processing technology of existing redundant metal filled regions and the processing results are not convenient for intelligent filling of redundant metals

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  • Redundancy metal filling region layout processing method and system
  • Redundancy metal filling region layout processing method and system
  • Redundancy metal filling region layout processing method and system

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Embodiment Construction

[0083] The following describes in detail the embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein the same or similar reference numerals refer to the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, but not to be construed as a limitation of the present invention.

[0084] Existing methods for layout processing of redundant metal-filled regions are usually based on density-based array indexing algorithms. The calculation speed of the array index algorithm is fast, but because the size of the array is heavily dependent on the layout processing parameters of the redundant metal filling area, when the set filling parameters are not suitable, it will lead to the phenomenon of missing filling, and the adjustability is poor.

[0085] A method and syst...

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Abstract

The present invention provides a redundancy metal filling region layout processing method and system. The method comprises the following steps: determining a condition on which a chemical mechanical planarization CMP process produces a process defect; determining a to-be-filled region according to the condition on which the CMP process produces the process defect; decomposing the to-be-filled region into simple geometric graphics; and generating a to-be-filled layout according to geometric information of each simple geometric graphic. The effect of a small-region geometric structure on the CMP defect is obtained according to a grinding theory of feature-level CMP, and the geometric information of the filled region is obtained by squaring processing of the layout, so that the problem that flatness can not be caused due to missing filling will not be caused, and intelligent filling of redundancy metal can be conveniently performed subsequently.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a method and system for processing a layout of a redundant metal filling area. Background technique [0002] With the continuous development of semiconductor technology, semiconductor process nodes are becoming smaller and smaller, and global planarization becomes more and more important. The chemical mechanical planarization (Chemical Mechanical Polishing, CMP) process is an important process for maintaining the global planarization of the chip surface in the manufacture of ultra-large-scale circuits. However, since media such as metals and oxides have different material removal rates during CMP, the CMP process itself leads to two types of planarity defects: metal dishing and oxide erosion. The redundant metal filling (DummyFill) technology is the main method to solve the above problems, and it is a hot issue that the industry and academia are generally concerned abo...

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F17/50
CPCG06F30/398
Inventor 曹鹤陈岚张贺
Owner INST OF MICROELECTRONICS CHINESE ACAD OF SCI