Finfet with multiple dislocation planes and method for forming same

Abstract

A device comprises a first semiconductor fin over a substrate, a second semiconductor fin over the substrate, wherein the first semiconductor fin and the second semiconductor fin are separated by a first isolation region, a first drain / source region coupled to the first semiconductor fin and the second semiconductor fin and a first dislocation plane underlying the first isolation region, wherein the first dislocation plane extends in a first direction in parallel with a longitudinal axis of the first semiconductor fin.

Description

technical field [0001] The present invention relates generally to the field of semiconductors, and more particularly to FinFET transistors. Background technique [0002] The semiconductor industry has experienced rapid development due to the ever-increasing integration density of various electronic components (eg, transistors, diodes, resistors, capacitors, etc.). For the most part, this increase in integration density stems from repeated reductions in minimum feature size, allowing more components to be integrated within a given area. However, smaller feature sizes can result in more leakage current. With the recent increase in demand for smaller electronic devices, it is necessary to reduce the leakage current of semiconductor devices. [0003] In a complementary metal-oxide-semiconductor (CMOS) field-effect transistor (FET), the active region consists of a drain, a source, a channel region connected between the drain and source, and the top of the channel to control the...

AI Technical Summary

Problems solved by technology

Short channel effects of conventional planar transistors have been reduced

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