Semiconductor chip packaging structure and manufacturing method thereof

Abstract

The invention provides a semiconductor chip packaging structure and a manufacturing method thereof. The method comprises the steps as follows: a plurality of electrodes which are arranged at intervals are formed on a semiconductor substrate; a sputtering conductive layer covering the semiconductor substrate and the electrodes is formed; an insulating protection layer is formed on the sputtering conductive layer outside the electrodes; the insulating protection layer comprises a first insulating protection block and a second insulating protection blocks, which are arranged at two sides of each electrode respectively; a metal layer and a soldering tin layer are sequentially formed on the sputtering conductive layer between each first insulating protection block and the corresponding second insulating protection block; and the sputtering conductive layer outside the first insulating protection blocks and the second insulating protection blocks is etched. In the manner, the undercut defect between the sputtering conductive layer and each metal layer can be avoided; the contact area of the sputtering conductive layer and each metal layer is increased; soldering tin is prevented from being injected into the sputtering conductive layer to form a mesoporous metal compound, so that the stability and the reliability of the semiconductor chip packaging structure are improved.

Description

technical field [0001] The invention relates to the field of semiconductor chip manufacturing, in particular to a semiconductor chip packaging structure and a manufacturing method thereof. Background technique [0002] figure 1 It is a schematic cross-sectional structure diagram of an existing semiconductor chip packaging structure. figure 2 yes figure 1 An enlarged view of the AA part of the package structure of the semiconductor chip shown. Such as figure 1 and figure 2 As shown, the semiconductor chip package structure includes a semiconductor substrate 1 , a plurality of electrodes 2 , a passivation layer 3 , a dielectric layer 4 , a sputtered conductive layer 5 , a metal layer 6 and solder metal terminals 7 . In the prior art, in the process of manufacturing the semiconductor chip package structure, it is necessary to etch the sputtered conductive layer 5 not covered by the metal layer 6 . During the etching process, the sputtered conductive layer 5 under the me...

AI Technical Summary

Problems solved by technology

During the etching process, the sputtered conductive layer 5 under the metal layer 6 is prone to over-etching, so that the remaining sputtered conductive layer 5 is recessed inward after the etching under the metal layer 6 to form undercut defects.

Wherein, the existence of the undercut defect will make the bottom part of the metal layer 6 suspended, thereby reducing the contact area between the metal layer 6 and the sputtered conductive layer 5, and reducing the connection strength between the metal layer 6 and the sputtered conductive layer 5. At this time, in Under the action of external force, there is a tendency to break between the metal layer 6 and the sputtered conductive layer 5, thereby affecting the stability and reliability of the semiconductor chip packaging structure

In addition, in the process of reflow forming the solder metal terminal 7, it is easy for the solder to inject into the sputtered conductive layer 5 through the undercut defect, so that the intermetallic compound reaction occurs between the solder and the sputtered conductive layer 5 to form an intermetallic compound interface. Under the action of external force, the intermetallic compound interface is easy to form cracks and break, which further affects the stability and reliability of the semiconductor chip packaging structure

Images