A self-selectable on-resistive memory device and its preparation method

Abstract

The invention discloses a self-selectable resistive memory device and a preparation method thereof. The self-selectable resistive memory device comprises: a lower electrode; an insulating medium layer, which is vertically intersected with the lower electrode to form a stacked structure. In the stacked structure A vertical trench is provided; a gating layer is grown on the lower electrode by self-alignment technology, wherein the interlayer leakage channel flowing through the gating layer is isolated by the insulating medium layer; a resistance conversion layer is set In the vertical groove, it is in contact with the insulating medium layer and the gate layer; the upper electrode is arranged in the resistance conversion layer. In the storage device provided by the above technical solution, the gate layer is grown on the lower electrode by self-alignment technology, so that the interlayer leakage channel flowing through the gate layer is isolated by the insulating medium layer, and the leakage of the upper and lower word lines through the gate layer is avoided. Therefore, the technical problem of electric leakage between upper and lower word lines of the self-selectable on-resistance memory device in the prior art is solved, and the reliability of the device is improved.

Description

technical field [0001] The invention relates to the technical field of microelectronics, in particular to a self-selectable on-resistance variable memory device and a preparation method thereof. Background technique [0002] The resistive variable memory is a metal / oxide / metal (MIM) capacitor structure, through the action of electrical signals, the device is reversible between the high resistance state (High Resistance State, HRS) and the low resistance state (Low Resistance State, LRS) Conversion, so as to realize the data storage function. Due to its excellent characteristics in terms of cell area, three-dimensional integration, low power consumption, high erasing and writing speed, and multi-value storage, it has attracted great attention at home and abroad. [0003] There are two main three-dimensional integration methods of resistive variable memory: one is the cross-array multilayer stacking structure, that is, the two-dimensional cross-array structure is repeatedly p...

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Problems solved by technology

Please refer to figure 2 , is the read / write schematic diagram of the vertical cross array. When reading / writing, there is a voltage difference of V / 2 (take the V / 2 bias mode as an example) between the upper and lower word lines. When the voltage difference between the layers is close to or exceeds the gate When the transition voltage of layer 501 is high, there will be a large leakage between the upper and lower word lines, which will cause device reliability problems

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