32 results about "Self gating" patented technology

Methods and software for self-gating a set of images. In exemplary embodiments, a fundamental heart frequency of the patient can be measured without the use of an ECG signal. In one method, the fundamental heart frequency can be determined by analyzing the size of the heart in the images. In another method, the fundamental heart frequency can be determined by applying a Fourier Transform. The measured fundamental heart frequency can thereafter be used to select slice images from the image scan for creation of a sagittal or coronal projection image. In exemplary embodiments, the resultant projection image can be used for coronary calcium detection and scoring.

A wave amplitude modulator for modulating a transmitted electromagnetic wave includes one or multiple self-gated capacitively coupled pair(s) of electron layers such as semiconductor or semimetal layers. Two electrical contacts are placed to each layer of electrons of the self-gated pair(s), and a power source is electrically connected to them. The power source, by varying the voltage applied between layers of electrons, tunes the electron density thereof, thereby adjusting the optical conductivity thereof, and the change in the optical conductivity of the layers of electrons causes an amplitude modulation of the transmitted electromagnetic wave passing through the capacitively coupled layers of electrons.

A clock gating cell for gating clock signals includes a latch circuit, a comparison logic circuit, a first logic circuit, and a second logic circuit. An input signal is provided to the latch circuit. An input clock signal is provided to the first logic circuit. The first logic circuit switches the input clock signal based on a comparison signal generated by the comparison logic circuit, thereby generating a latch clock signal. The latch clock signal switches between a first state and a second state only when the input signal switches between the first state and the second state, thereby preventing power loss of the clock gating cell.

A method for identifying and removing redundant signal paths includes determining whether a given input to a logic circuit is coupled to both an input of a cone of logic of a data input of a clocked state element and a clock gate circuit that is coupled to disable a clock input to the clocked state element. The method may include removing the given input from the cone of logic such that the given input is no longer coupled to the input of the cone of logic responsive to determining that the given input is coupled to both the input of the cone of logic and the clock gate circuit. The method may include preserving the given input to the clock gate circuit such that the given input continues to be coupled to the clock gate circuit after being removed from the input of the cone of logic.

A circuit includes a voltage-to-current converter receives a first voltage and a second voltage and outputs a first current and a second current in accordance with a clock signal. A first self-gated cascode circuit receives the first current and outputs a third current in accordance with the clock signal. A second self-gated cascode circuit receives the second current and outputs a fourth current in accordance with the clock signal. A latch circuit receives the third current and the fourth current and establishes a third voltage and a fourth voltage representing a resolution of a comparison between the third current and the fourth current, wherein the first self-gated cascode circuit is conditionally shut off based on a level of the third voltage, and the second self-gated cascode circuit is conditionally shut off based on a level of the fourth voltage.

The invention discloses a self-selectable resistive memory device and a preparation method thereof. The self-selectable resistive memory device comprises: a lower electrode; an insulating medium layer, which is vertically intersected with the lower electrode to form a stacked structure. In the stacked structure A vertical trench is provided; a gating layer is grown on the lower electrode by self-alignment technology, wherein the interlayer leakage channel flowing through the gating layer is isolated by the insulating medium layer; a resistance conversion layer is set In the vertical groove, it is in contact with the insulating medium layer and the gate layer; the upper electrode is arranged in the resistance conversion layer. In the storage device provided by the above technical solution, the gate layer is grown on the lower electrode by self-alignment technology, so that the interlayer leakage channel flowing through the gate layer is isolated by the insulating medium layer, and the leakage of the upper and lower word lines through the gate layer is avoided. Therefore, the technical problem of electric leakage between upper and lower word lines of the self-selectable on-resistance memory device in the prior art is solved, and the reliability of the device is improved.

Provided are a self-gating resistive storage device and a method for fabrication thereof; said self-gating resistive storage device comprises: lower electrodes; insulating dielectric layers arranged perpendicular to, and intersecting with, the lower electrodes to form a stacked structure, said stacked structure being provided with a vertical trench; a gating layer grown on the lower electrodes by means of self-alignment technique, the interlayer leakage channel running through the gating layer being isolated via the insulating dielectric layers; a resistance transition layer arranged in the vertical trench and connected to the insulating dielectric layers and the gating layer; and an upper electrode arranged in the resistance transition layer. In the storage device provided by the described technical solution, the gating layer is grown on the lower electrodes by means of self-alignment technique, such that the interlayer leakage channel running through the gating layer is isolated via the insulating dielectric layers; thus leakage between the upper and lower word lines through the gating layer is prevented, solving the technical problem in the prior art of leakage between the upper and lower word lines in a self-gating resistive storage device, and improving the reliability of the device.

The invention provides a motion signal extracting method and device for self-gating three-dimensional cardiac imaging, and relates to the technical field of three-dimensional cardiac imaging. The method includes the steps that according to the TureFISP sequence, cardiac cine imaging data are obtained by adopting a multi-echo three-dimensional radial mixed collecting mode; signal values of multiple points are obtained from radial sampling lines of all collecting layers in the cardiac cine imaging data, and average values of the signal values of the multiple points are determined to serve as navigation signals; the navigation signals are subjected to inverse Fourier transformation to be transformed into an image domain, and heartbeat and breathing motion mixed signals are obtained through weighting; the heartbeat and breathing motion mixed signals are filtered through a band-pass filter to obtain heartbeat signals and breath signals; according to the heartbeat signals and the breath signals, the cardiac cine imaging data are arrayed and synchronized again to generate three-dimensional cardiac images. The problem that in the prior art, the quality of the rebuilt cardiac cine images is affected as obtained motion signals are inaccurate is solved.

The invention discloses a super computing system oriented self-gating boundary scan test method and a super computing system oriented self-gating boundary scan test device. The method comprises the following steps of: calculating to obtain the optimum test joint test action group (JTAG) line according to an input target main board number, a test command and test concurrency to determine a JTAG output port of a monitoring main board and send a control signal; and receiving the control signal of a JTAG gate by using a crossbar network on a rear panel, and changing turn-on and turn-off of each switch in the crossbar switch network according to the control signal to finish gating and executing a test command by using the gated JTAG output port. The device comprises a JTAG controller and the JTAG gate which are positioned on the monitoring main board, and a crossbar switch network module positioned on the rear panel. The method and the device have the advantages of simple structure, few rear panel wire, high test flexibility, high test efficiency and balanced JTAG line load.

The invention discloses an activity similarity based trigger grouping clock gating method. The method includes the following steps: acquiring an activity vector of each trigger in a typical working mode on the basis of gate level simulation in a typical working mode of a kernel of a digital signal processor, and acquiring the transition rate of the triggers and the correlation among the triggers by counting and processing the activity vectors of the triggers; performing initial layout by using a layout tool, and acquiring initial positions of the triggers in the kernel of the digital signal processor in a layout; and achieving grouping of the triggers by using transition rate information and trigger position data; achieving clock gating through trigger grouping information and the XOR gate self-gating method; and making a new layout for new generated net lists, and achieving clock tree comprehensive and power consumption simulation verification. The method can achieve trigger grouping clock gating of the kernel of the digital signal processor, can effectively prolong the gating period of a clock, and can reduce the dynamic power consumption.

An n-bit counter is formed from cascading counter sub-modules. The counter includes combinatorial control logic coupled to a lower order counter sub-module. The control logic is arranged to clock gate at least one higher order counter sub-module dependent on a logical combination of outputs of the lower order counter sub-module and where the control logic uses pipelining to store at least one previous control logic output for use in determining a later control logic output.

A method and apparatus for self gate pumped NMOS high speed switch have been disclosed.