31 results about "Self gating" patented technology

Methods and software for self-gating a set of images. In exemplary embodiments, a fundamental heart frequency of the patient can be measured without the use of an ECG signal. In one method, the fundamental heart frequency can be determined by analyzing the size of the heart in the images. In another method, the fundamental heart frequency can be determined by applying a Fourier Transform. The measured fundamental heart frequency can thereafter be used to select slice images from the image scan for creation of a sagittal or coronal projection image. In exemplary embodiments, the resultant projection image can be used for coronary calcium detection and scoring.

A wave amplitude modulator for modulating a transmitted electromagnetic wave includes one or multiple self-gated capacitively coupled pair(s) of electron layers such as semiconductor or semimetal layers. Two electrical contacts are placed to each layer of electrons of the self-gated pair(s), and a power source is electrically connected to them. The power source, by varying the voltage applied between layers of electrons, tunes the electron density thereof, thereby adjusting the optical conductivity thereof, and the change in the optical conductivity of the layers of electrons causes an amplitude modulation of the transmitted electromagnetic wave passing through the capacitively coupled layers of electrons.

The invention discloses a self-gating resistive random-access memory device and a preparation method thereof. The self-gating resistive random-access memory device includes: a lower electrode; an insulating medium layer which is in perpendicular crossing arrangement with the lower electrode so as to form a stacked composition. The stacked composition is provided therein with a vertical groove; a gating layer which is generated on the lower electrode through a self-alignment technique, in which an interlayer electric leakage channel which passes by the gating layer is isolated by the insulating medium layer; a resistance transferring layer which is disposed inside the vertical groove and is connected to the insulating medium layer and the gating layer; an upper electrode which is arranged inside the resistance transferring layer. The memory device provided by the technical solution, generates the gating layer on the lower electrode through the self-alignment technique, allows the interlayer electric leakage channel which passes the gating layer to be insulated by the insulating medium layer, and prevents upper and lower word lines from leaking electricity through the gating layer, which address the problem of electric leakage among the upper and lower word lines of the self-gating resistive random-access memory device and increase reliability of the device.

A clock gating cell for gating clock signals includes a latch circuit, a comparison logic circuit, a first logic circuit, and a second logic circuit. An input signal is provided to the latch circuit. An input clock signal is provided to the first logic circuit. The first logic circuit switches the input clock signal based on a comparison signal generated by the comparison logic circuit, thereby generating a latch clock signal. The latch clock signal switches between a first state and a second state only when the input signal switches between the first state and the second state, thereby preventing power loss of the clock gating cell.

A synchronizer circuit for transferring data from a source clock domain to a target clock domain. A first latch in the target clock domain may capture a data value corresponding to current data received from the source clock domain. Under certain conditions, the first latch may enter into a metastable, or undefined logic state. A second latch may remain stable, and store a previous value corresponding to data that has most recently been transferred from the source clock domain to the target clock domain. The respective values output by the two latches may be compared by a detection circuit, and a value derived from the output value of the first latch and corresponding to the current data may be written to an output latch if the current data differs from the stored previous value. The detection circuit may also provide a defined logical value to the output latch even if the first latch is in a metastable state.

An n-bit counter is formed from cascading counter sub-modules. The counter includes combinatorial control logic coupled to a lower order counter sub-module. The control logic is arranged to clock gate at least one higher order counter sub-module dependent on a logical combination of outputs of the lower order counter sub-module and where the control logic uses pipelining to store at least one previous control logic output for use in determining a later control logic output.

The invention relates to a resistive layer self-gating resistive random access memory as well as a building method and application thereof. The resistive random access memory comprises an overlappinglayer, wherein the overlapping layer comprises a fourth Hf layer, a fourth Si<3>N<4> layer, a third Hf layer, a third Si<3>N<4> layer, a second Hf layer, a second Si<3>N<4> layer, a first Hf layer anda first Si<3>N<4> layer which are arranged in sequence from outside to inside. During 1R array gating based on a homogeneous HfO<x> base, a resistive layer is taken as a gating layer, so that an extra third gating device is prevented from being introduced. An asymmetrical structure is machined based on micro-nano for filling (or hollowing), a depletion region is formed on the periphery of a filling region under the micro-nano scale, and the depletion region dynamically changes along with an external electric field. A self-gating effect is achieved according to the universal physical principle. Thus, the resistive random access memory is not limited to the HfO<x> material, but also suitable for all materials capable of forming the depletion region.

The invention discloses an activity similarity based trigger grouping clock gating method. The method includes the following steps: acquiring an activity vector of each trigger in a typical working mode on the basis of gate level simulation in a typical working mode of a kernel of a digital signal processor, and acquiring the transition rate of the triggers and the correlation among the triggers by counting and processing the activity vectors of the triggers; performing initial layout by using a layout tool, and acquiring initial positions of the triggers in the kernel of the digital signal processor in a layout; and achieving grouping of the triggers by using transition rate information and trigger position data; achieving clock gating through trigger grouping information and the XOR gate self-gating method; and making a new layout for new generated net lists, and achieving clock tree comprehensive and power consumption simulation verification. The method can achieve trigger grouping clock gating of the kernel of the digital signal processor, can effectively prolong the gating period of a clock, and can reduce the dynamic power consumption.

The invention provides a motion signal extracting method and device for self-gating three-dimensional cardiac imaging, and relates to the technical field of three-dimensional cardiac imaging. The method includes the steps that according to the TureFISP sequence, cardiac cine imaging data are obtained by adopting a multi-echo three-dimensional radial mixed collecting mode; signal values of multiple points are obtained from radial sampling lines of all collecting layers in the cardiac cine imaging data, and average values of the signal values of the multiple points are determined to serve as navigation signals; the navigation signals are subjected to inverse Fourier transformation to be transformed into an image domain, and heartbeat and breathing motion mixed signals are obtained through weighting; the heartbeat and breathing motion mixed signals are filtered through a band-pass filter to obtain heartbeat signals and breath signals; according to the heartbeat signals and the breath signals, the cardiac cine imaging data are arrayed and synchronized again to generate three-dimensional cardiac images. The problem that in the prior art, the quality of the rebuilt cardiac cine images is affected as obtained motion signals are inaccurate is solved.

Provided are a self-gating resistive storage device and a method for fabrication thereof; said self-gating resistive storage device comprises: lower electrodes; insulating dielectric layers arranged perpendicular to, and intersecting with, the lower electrodes to form a stacked structure, said stacked structure being provided with a vertical trench; a gating layer grown on the lower electrodes by means of self-alignment technique, the interlayer leakage channel running through the gating layer being isolated via the insulating dielectric layers; a resistance transition layer arranged in the vertical trench and connected to the insulating dielectric layers and the gating layer; and an upper electrode arranged in the resistance transition layer. In the storage device provided by the described technical solution, the gating layer is grown on the lower electrodes by means of self-alignment technique, such that the interlayer leakage channel running through the gating layer is isolated via the insulating dielectric layers; thus leakage between the upper and lower word lines through the gating layer is prevented, solving the technical problem in the prior art of leakage between the upper and lower word lines in a self-gating resistive storage device, and improving the reliability of the device.

The invention discloses a self-gating device of a two-dimensional molybdenum oxide/molybdenum sulfide laminated structure and a manufacturing method of the self-gating device, and relates to the technical field of microelectronics. The self-gating device comprises an upper electrode layer, a lower electrode layer and a functional layer, wherein a functional layer material is located between the upper electrode layer and the lower electrode layer, the functional layer is formed by sequentially stacking a dielectric layer I and a dielectric layer II, the dielectric layer I is two-dimensional molybdenum oxide (alpha-MoO3), and the dielectric layer II is a semiconductor material of two-dimensional molybdenum sulfide (MoS2). Compared with the prior art, the self-gating device formed in a lamination mode solves the crosstalk problem in a cross integrated array under the condition that the occupied area is not enlarged; and the stacked structure of the dielectric layer I and the dielectric layer II realizes self-gating performance, shows good nonlinear characteristic, has the nonlinearity of 10<5>, and is extremely high in miniaturization, simple in process and cost-saving.

Systems, apparatuses, and methods for implementing stripe-based self-gating and change detect signal propagation for retiming pipelines are disclosed. A circuit includes one or more stripes, with each stripe including a plurality of stages of registers, with each stage only receiving input signals from the preceding stage. For a given stripe, the first stage of registers are self-gated to reduce power consumption by only clocking a group of registers when any of their input signals change. The self-gating signals of the first stage of registers are combined together to create a change detect signal which is passed through a register and provided to a second stage of registers as a clock-enable signal. Accordingly, the second stage registers are only clocked when the change detect signal indicates a change will be forwarded from the first stage. This reduces power consumption for the second stage without causing the area increase associated with self-gating circuitry.

A method and apparatus for self gate pumped NMOS high speed switch have been disclosed.