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Self-gating device based on two-dimensional molybdenum oxide/molybdenum sulfide laminated structure and manufacturing method thereof

A stacked structure and manufacturing method technology, applied in the field of microelectronics, can solve the problems of unguaranteed deposition uniformity and complicated process, and achieve the effects of reducing power consumption, strong miniaturization, and reducing leakage current

Active Publication Date: 2021-08-10
TIANJIN UNIVERSITY OF TECHNOLOGY
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

CN 104485418 A discloses a method for preparing a self-gating device with a vertical trench structure. A multilayer electrode stack structure is used to deposit a gating layer on the inner wall and bottom of the groove. The process is complicated and the deposition uniformity cannot be guaranteed

Method used

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  • Self-gating device based on two-dimensional molybdenum oxide/molybdenum sulfide laminated structure and manufacturing method thereof
  • Self-gating device based on two-dimensional molybdenum oxide/molybdenum sulfide laminated structure and manufacturing method thereof
  • Self-gating device based on two-dimensional molybdenum oxide/molybdenum sulfide laminated structure and manufacturing method thereof

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Embodiment approach

[0022] The invention discloses an embodiment of a method for manufacturing a self-gated device based on a two-dimensional material stack structure, which includes the following steps:

[0023] In the first step, the pattern of the lower electrode is exposed on the substrate 100, the lower electrode 101 is prepared by physical vapor deposition, and the patterned lower electrode 101 is obtained by lift-off. Such as figure 2 shown;

[0024] In the second step, based on the surface of the lower electrode 101, the dielectric layer I102 is grown in situ by magnetron sputtering combined with post-annealing process, such as image 3 shown;

[0025] In the third step, based on the surface transfer of the dielectric layer I102, nanosheets are prepared by chemical vapor deposition as the dielectric layer II103, such as Figure 4 shown;

[0026] The fourth step is to pattern the upper electrode based on the surface alignment exposure of the dielectric layer II 103, deposit the upper ...

Embodiment 2

[0033] The invention discloses an embodiment of a method for manufacturing a self-gated device based on a two-dimensional material stack structure, which includes the following steps:

[0034] In the first step, based on the surface of the substrate 100, gold is deposited as the lower electrode 101 by physical vapor deposition method, with a thickness of 100 nm, the mask pattern of the lower electrode is exposed, and the patterned lower electrode 101 is obtained through a dry etching process;

[0035] In the second step, based on the surface of the lower electrode 101, a dielectric layer I 102 is grown in-situ with a thickness of 3 nm by using a combination of atomic layer deposition and post-annealing processes;

[0036] The third step is to peel off the bulk material based on the surface of the dielectric layer I102 as the dielectric layer II103 with a thickness of 20nm;

[0037] The fourth step is to pattern the upper electrode based on the surface alignment exposure of the...

Embodiment 3

[0039] The invention discloses an embodiment of a method for manufacturing a self-gated device based on a two-dimensional material stack structure, which includes the following steps in sequence:

[0040] In the first step, based on the method of physical vapor deposition above the substrate 100, chromium is prepared as the lower electrode 101 with a thickness of 80nm, and the patterned lower electrode 101 is obtained through an etching process;

[0041] In the second step, the dielectric layer I102 is grown by chemical vapor deposition and transferred to the surface of the lower electrode 101, with a thickness of 10 nm;

[0042] In the third step, the dielectric layer II 103 is grown by chemical vapor deposition method and transferred to the surface of the lower dielectric layer I 102 in precise alignment, with a thickness of 6 nm;

[0043] The fourth step is to pattern the upper electrode based on the surface alignment exposure of the dielectric layer II 103, and deposit tungs...

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Abstract

The invention discloses a self-gating device of a two-dimensional molybdenum oxide / molybdenum sulfide laminated structure and a manufacturing method of the self-gating device, and relates to the technical field of microelectronics. The self-gating device comprises an upper electrode layer, a lower electrode layer and a functional layer, wherein a functional layer material is located between the upper electrode layer and the lower electrode layer, the functional layer is formed by sequentially stacking a dielectric layer I and a dielectric layer II, the dielectric layer I is two-dimensional molybdenum oxide (alpha-MoO3), and the dielectric layer II is a semiconductor material of two-dimensional molybdenum sulfide (MoS2). Compared with the prior art, the self-gating device formed in a lamination mode solves the crosstalk problem in a cross integrated array under the condition that the occupied area is not enlarged; and the stacked structure of the dielectric layer I and the dielectric layer II realizes self-gating performance, shows good nonlinear characteristic, has the nonlinearity of 10<5>, and is extremely high in miniaturization, simple in process and cost-saving.

Description

technical field [0001] The invention relates to the field of microelectronic technology, in particular to a self-selecting device based on a two-dimensional molybdenum oxide / molybdenum sulfide laminated structure and a manufacturing method thereof. Background technique [0002] Resistive RAM (RRAM) is a next-generation storage device with considerable potential that can compete with mainstream flash memory. The cross-array structure of RRAM is considered to be the most economical integration method with the smallest unit area in the memory, but the challenge faced in the high-density integration of RRAM devices is the phenomenon of crosstalk. Therefore, we need each cell to have a rectification feature to avoid misreading in the array structure. At present, the commonly used gating methods in the semiconductor process include field effect transistors connected in series with resistive cells (1T1R), rectifier diodes connected in series with resistive cells (1D1R), nonlinear ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L45/00
CPCH10N70/20H10N70/8822H10N70/883H10N70/011Y02P70/50
Inventor 张楷亮单欣王芳胡凯林欣赵轩宇吴泽宇李微
Owner TIANJIN UNIVERSITY OF TECHNOLOGY
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