A trigger group clock gating method based on activity similarity

Abstract

The invention discloses an activity similarity based trigger grouping clock gating method. The method includes the following steps: acquiring an activity vector of each trigger in a typical working mode on the basis of gate level simulation in a typical working mode of a kernel of a digital signal processor, and acquiring the transition rate of the triggers and the correlation among the triggers by counting and processing the activity vectors of the triggers; performing initial layout by using a layout tool, and acquiring initial positions of the triggers in the kernel of the digital signal processor in a layout; and achieving grouping of the triggers by using transition rate information and trigger position data; achieving clock gating through trigger grouping information and the XOR gate self-gating method; and making a new layout for new generated net lists, and achieving clock tree comprehensive and power consumption simulation verification. The method can achieve trigger grouping clock gating of the kernel of the digital signal processor, can effectively prolong the gating period of a clock, and can reduce the dynamic power consumption.

Description

technical field [0001] The invention relates to the field of dynamic power consumption reduction in DSP low power consumption technology, in particular to a gate-level clock gating method. Background technique [0002] Digital Signal Processor (DSP) is a microprocessor that is especially suitable for digital signal processing operations, and its main application is to realize various digital signal algorithms in real time and quickly. Just because of its powerful signal processing capability and fast signal processing speed, DSP is widely used in various fields such as industry, communication, and military affairs. [0003] With the development of various fields, the complexity of chip design has also increased significantly, and the requirements for DSP chips are increasingly developing in the direction of small size, low power consumption, and high performance, but higher computing speeds will inevitably lead to increase in power consumption. Especially for portable hand...

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Problems solved by technology

However, synthesis tools mainly realize the gate control of some flip-flops through the derivation of logic functions, so it is difficult to guarantee high clock gating efficiency.

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