Self-gating Resistive Random-Access Memory device and preparation method thereof

Abstract

The invention discloses a self-gating resistive random-access memory device and a preparation method thereof. The self-gating resistive random-access memory device includes: a lower electrode; an insulating medium layer which is in perpendicular crossing arrangement with the lower electrode so as to form a stacked composition. The stacked composition is provided therein with a vertical groove; a gating layer which is generated on the lower electrode through a self-alignment technique, in which an interlayer electric leakage channel which passes by the gating layer is isolated by the insulating medium layer; a resistance transferring layer which is disposed inside the vertical groove and is connected to the insulating medium layer and the gating layer; an upper electrode which is arranged inside the resistance transferring layer. The memory device provided by the technical solution, generates the gating layer on the lower electrode through the self-alignment technique, allows the interlayer electric leakage channel which passes the gating layer to be insulated by the insulating medium layer, and prevents upper and lower word lines from leaking electricity through the gating layer, which address the problem of electric leakage among the upper and lower word lines of the self-gating resistive random-access memory device and increase reliability of the device.

Description

technical field [0001] The invention relates to the technical field of microelectronics, in particular to a self-selectable on-resistance variable memory device and a preparation method thereof. Background technique [0002] The resistive variable memory is a metal / oxide / metal (MIM) capacitor structure. Through the action of electrical signals, the device is reversibly switched between the high resistance state (HighResistanceState, HRS) and the low resistance state (LowResistanceState, LRS), thereby realizing data storage capabilities. Due to its excellent characteristics in terms of cell area, three-dimensional integration, low power consumption, high erasing and writing speed, and multi-value storage, it has attracted great attention at home and abroad. [0003] There are two main three-dimensional integration methods of resistive variable memory: one is the cross-array multilayer stacking structure, that is, the two-dimensional cross-array structure is repeatedly prepar...

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Problems solved by technology

Please refer to figure 2 , is the read / write schematic diagram of the vertical cross array. When reading / writing, there is a voltage difference of V / 2 (take the V / 2 bias mode as an example) between the upper and lower word lines. When the voltage difference between the layers is close to or exceeds the gate When the transition voltage of layer 501 is high, there will be a large leakage between the upper and lower word lines, which will cause device reliability problems

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