integrated circuit device

Abstract

The present disclosure provides integrated circuit devices. An integrated circuit device includes: a source / drain region having a recess in its top; a contact plug extending from inside the recess on the source / drain region; and a metal silicide layer serving as The liner is recessed and has a first portion covering the bottom surface of the contact plug and a second portion integral with the first portion and covering the lower portion of the side of the contact plug. The second portion of the silicide layer may have a different thickness than the thickness of the first portion of the silicide layer. The silicide layer is formed at a relatively low temperature to provide improved resistance characteristics between the source / drain regions and the contact plugs.

Description

technical field [0001] The inventive concept relates to integrated circuit devices and methods of fabricating the integrated circuit devices. More particularly, the inventive concepts relate to integrated circuit devices including fin field effect transistors and methods of fabricating the integrated circuit devices. Background technique [0002] Increasing the integration density of integrated circuit devices including field-effect transistors (FETs), including by reducing the gate length of field-effect transistors (FETs), can compromise certain performance characteristics of the devices, especially in horizontal (planar) metal oxide In the case of a material semiconductor FET (MOSFET). To overcome these limitations, devices with three-dimensional channels such as fin FETs (FinFETs) are being developed. However, the scaling of FinFETs creates its own challenges. For example, the contact resistance between the source and drain regions of a FinFET and conductive contact p...

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Problems solved by technology

However, the scaling of FinFETs poses its own challenges

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