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Apparatuses, memories, and methods for address decoding and selecting access line

An address decoder and selection line technology, which is applied to equipment, memory and fields for address decoding and selection of access lines, can solve problems such as increase in cost and space

Active Publication Date: 2016-08-31
MICRON TECH INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The increase in cost and space required for conventional decoder architectures may be undesirable in applications where compact and simple circuitry is required

Method used

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  • Apparatuses, memories, and methods for address decoding and selecting access line
  • Apparatuses, memories, and methods for address decoding and selecting access line
  • Apparatuses, memories, and methods for address decoding and selecting access line

Examples

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Embodiment Construction

[0013] Certain details are set forth below in order to provide a thorough understanding of embodiments of the invention. It will be apparent, however, to one skilled in the art that the embodiments of the invention may be practiced without employing these specific details. Furthermore, specific embodiments of the invention described herein are provided by way of example and should not be used to limit the scope of the invention to these specific embodiments. In other instances, well-known circuits, control signals, timing protocols and software operations have not been shown in detail in order to avoid unnecessarily obscuring the present invention.

[0014] figure 1 A device 100 including an address decoder 104 according to an embodiment of the invention is illustrated. The apparatus may be an integrated circuit, a memory device, a memory system, and the like. Address decoder 104 may be configured to decode addresses to select access lines for activation. Address decoder 1...

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PUM

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Abstract

Apparatuses, memories, and methods for decoding memory addresses for selecting access lines in a memory are disclosed. An example apparatus includes an address decoder circuit coupled to first and second select lines, a polarity line, and an access line. The first select line is configured to provide a first voltage, the second select line is configured to provide a second voltage, and the polarity line is configured to provide a polarity signal. The address decoder circuit is configured to receive address information and further configured to couple the access line to the first select line responsive to the address information having a combination of logic levels and the polarity signal having a first logic level, and further configured to couple the access line to the second select line responsive to the address information having the combination of logic levels and the polarity signal having a second logic level.

Description

Background technique [0001] Conventional memory systems may include low voltage select lines and high voltage deselect lines for accessing desired word lines or bit lines (commonly referred to as memory access lines). Selected memory access lines in the array are coupled to select lines, and unselected memory access lines are coupled to deselect lines. Conventional two transistor decoder circuits used to select memory access lines may include p-channel field effect (PFET) transistors and n-channel field effect (NFET) transistors. NFET transistors can be advantageously used to deliver low voltages, and PFET transistors can be advantageously used to deliver high voltages. In the example conventional system described, the circuit works most efficiently when the NFET transistor connects the access line to the active select line and when the PFET transistor connects the access line to the active deselect line. [0002] However, for some memory technologies, such as bipolar resist...

Claims

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Application Information

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IPC IPC(8): G11C8/10G11C8/14
CPCG11C13/0069G11C8/08G11C8/10G11C13/0026G11C13/0028G11C13/0023G11C13/004
Inventor 斯蒂芬·H·唐
Owner MICRON TECH INC
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