Method and apparatus for adjusting phases of EMMC interface and NAND interface

Abstract

The present invention provides a method and an apparatus for adjusting phases of an EMMC interface and a NAND interface. The method comprises that before a first normal operation mode, adaptive training is carried out on a PCB board, and test stimulus data is sent out according pre-stored transmission clock frequency of a data sequence, and after undergoing a two-stage register delay, the data is sent to a data pin port of a master chip, and is transmitted through a PCB wire to a data pin of the EMMC or the NAND device; simultaneously, after sequentially undergoing a phase delay and the two-stage register delay, a data transmission clock of the EMMC or the NAND is output to a clock pin port of the master chip, and is transmitted through the PCB wire to a clock pin of the EMMC or the NAND device; and the phase delay and the two-stage register delay are controlled until a chip exterior phase delay chip configuration optimally matched with the PCB board level phase delay, so as to enable the master chip to carry out EMMC or NAND data transmission during normal operation. Thus, optimal match effects under different PCB electrical conditions can be reached.

Description

technical field [0001] The invention relates to a chip interface technology, in particular to a phase adaptive adjustment method and device for an EMMC chip interface and a NAND flash memory interface. Background technique [0002] EMMC (Embedded Multi Media Card) is an embedded memory standard specification established by the MMC Association, mainly for products such as mobile phones or tablet computers. A clear advantage of eMMC is the integration of a controller in the package, which provides a standard interface and manages the flash memory, freeing handset manufacturers to focus on other parts of product development and reducing time-to-market. [0003] EMMC is a commonly used data communication interface at present, and is widely used in the communication between various chips. However, due to the high transmission speed of EMMC, and the data receiving end needs to use the received clock to sample the received data, so this has a great impact on the PCB layout. The bo...

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Problems solved by technology

However, due to the high transmission speed of the nand flash memory interface, and at the same time, the data receiving end needs to use the received clock to sample the received data, so this has high requirements for the PCB layout, and it is necessary to pay great attention to the trace length of the clock and data wires , otherwise it is easy to cause the clock and data phases sent by the sending end to be correct, but when they arrive at the receiving end after being delayed by PCB traces, the phases of the receiving clock and received data change and do not meet the sampling timing requirements, eventually resulting in wrong sampling

At the same time, due to the different output phases of the nand flash interface of different chips, different PCB routing needs to be designed for the nand flash interface of different chips, and it is impossible to make one circuit board universally adaptable to the nand flash memory of different chips, resulting in a large material resource and waste of human resources

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