Method and device for self-adaptive adjustment of i2s peripheral circuit timing
A technology of self-adaptive adjustment and peripheral circuit, which is applied in the direction of electrical digital data processing and instruments, to achieve the effects of reducing design difficulty, improving robustness, and high adjustment accuracy
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[0065] Such as figure 2 As shown, the adaptive adjustment method of I2S peripheral circuit timing of the present invention comprises the following steps:
[0066] (1) Carry out adaptive training on the PCB board before the first normal working mode, and first set the test mode signal to be valid;
[0067] (2) The test stimulus data is strobed and sent out according to the transmission clock frequency of the pre-stored data sequence, and then sent to the data pin port of the main control chip after being delayed by the two-stage register, and then transmitted to the data of the I2S device through the PCB wire pin feet; at the same time
[0068] The data transmission clock of the I2S device is output to the clock pin port of the main control chip after phase delay and register delay in sequence, and then transmitted to the clock pin of the I2S device through the PCB wire;
[0069] (3) by controlling the phase delay and the register delay, until the internal phase delay config...
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