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Programmable delay circuit with integer and fractional time resolution

A delay circuit and time-resolution technology, applied in electrical components, pulse technology, pulse processing, etc., can solve problems such as different propagation delays of clock signals

Active Publication Date: 2021-04-06
QUALCOMM INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The data signal and the clock signal may have different propagation delays and may not be time aligned at synchronous circuits

Method used

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  • Programmable delay circuit with integer and fractional time resolution
  • Programmable delay circuit with integer and fractional time resolution
  • Programmable delay circuit with integer and fractional time resolution

Examples

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Embodiment Construction

[0017] The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any exemplary embodiment described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other exemplary embodiments.

[0018] The programmable delay circuits described herein can be used to match the delay of signals provided to synchronous circuits such as flip-flops, latches, and the like. The programmable delay circuit can be used in an interface circuit between different devices, such as a CPU and a memory, which can be implemented on the same integrated circuit (IC) or on different ICs. The programmable delay circuit can also be used for internal circuitry within a given device or IC.

[0019] figure 1 A block diagram of device 100 with CPU 110 and memory 120 and 130 is shown. CPU 110 may include any type of processor, such as a digital signal processor (DSP), a general purpose processor, a microprocessor, a Reduced Instruction S...

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Abstract

The present invention describes a programmable delay circuit capable of providing delays with integer and fractional time resolution. In one exemplary design, an apparatus includes first and second delay circuits. The first delay circuit provides a first delay of an integer number of time units. The second delay circuit is coupled to the first delay circuit and provides a second delay that is a fraction of a unit of time. The first delay circuit may include a plurality of unit delay cells coupled in series. Each unit delay unit may provide a delay of one time unit when enabled. The second delay circuit may have first and second paths. The first path may provide a shorter delay when selected, and the second path may provide a longer delay when selected. The second path may be coupled to at least one dummy logic gate providing additional loading to obtain the longer delay of the second path.

Description

[0001] Information about divisional applications [0002] The application number of this application is PCT / US2008 / 087545, the application date is December 18, 2008, the priority date is December 20, 2007, and the title of the invention is "programmable delay circuit with integer and fractional time resolution" The divisional application of the Chinese invention patent application with the application number 200880121419.5 after the PCT application entered the national phase. technical field [0003] The present invention relates generally to electronic circuits and, more particularly, to delay circuits. Background technique [0004] A synchronous circuit, such as a flip-flop or a latch, may receive a data signal from one source and a clock signal from another source. The data signal and the clock signal may have different propagation delays and may not be time aligned at synchronous circuits. It may be desirable to delay the clock signal and / or the data signal by some su...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H03K5/131
CPCH03K5/131
Inventor 穆斯塔法·克斯金马尔奇奥·佩德拉里-诺伊
Owner QUALCOMM INC