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Test method for multiplier of embedded DSP in FPGA

A test method and multiplier technology, applied in digital circuit testing, electronic circuit testing, instruments, etc., can solve problems such as testing that cannot achieve high coverage, and achieve low cost, strong scalability, and good portability Effect

Active Publication Date: 2016-10-12
FUDAN UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

However, the test method proposed in [7] is still for the Wallace tree structure composed of full adder and half adder, for the 4-2 compressor, 7-3 compressor, 11-4 compressor [8 ][9] and other Wallace tree structures cannot achieve high coverage tests

Method used

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  • Test method for multiplier of embedded DSP in FPGA
  • Test method for multiplier of embedded DSP in FPGA
  • Test method for multiplier of embedded DSP in FPGA

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Experimental program
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Embodiment approach

[0039] For multipliers of various structures, the present invention can provide a test vector set with high coverage. Based on a kind of embedded DSP in FPGA proposed in the literature [8] Take the multiplier structure as an example. The multiplier proposed is a multiplier with a Wallace tree structure using Booth2 encoding, and its compression tree structure is complex. The compressors that make up the compression tree are half adder, 11-4 compressor, 7-3 compressor, 4-2 compressor and 3-2 compressor. For this multiplier, the specific implementation of the present invention is as follows:

[0040] First, it is necessary to describe the structure of the Wallace tree in the multiplier according to the format required by the present invention. According to the compressor description format given in Table 1, describe all compressors in the compression tree. E.g, image 3 An example of a 7-3 compressor description is given in. After all the compressor descriptions are completed...

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Abstract

The invention discloses a test method for a multiplier of an embedded DSP in an FPGA, and belongs to the technical field of integrated circuits. A method to define a description manner of a compression circuit structure of the multiplier and generate an optimal test vector set automatically is included, and the vector set can be used to realize high fault coverage rate and short test time. The optimal test vector set can be provided for the multiplier of the given coding manner and the part backlog compression circuit structure automatically. The embedded DSP in the FPGA can be test effectively. The test method is characterized by high fault coverage rate, low cost, high transportability and high versatility.

Description

Technical field [0001] The invention belongs to the technical field of integrated circuits, and specifically relates to a method for testing an embedded DSP internal multiplier in an FPGA. Background technique [0002] As Field Programmable Gate Array (Field Programmable Gate Array, FPGA) becomes more widely used, people have higher and higher requirements for FPGA performance and capacity. By embedding multiple IP cores in the FPGA, the performance and application range of the FPGA can be greatly improved. Therefore, the position of embedded IP core in FPGA is becoming more and more important. Among them, DSP has been widely embedded in modern FPGA because of its ability to process data at high speed, and has become an important part of FPGA. [0003] Embedded DSP in FPGA is mainly composed of adder and multiplier. Among them, the multiplier is mainly composed of two parts, one part is a partial product generation circuit, and the other part is a partial product compression cir...

Claims

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Application Information

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IPC IPC(8): G01R31/3181G01R31/317
CPCG01R31/31707G01R31/3181
Inventor 来金梅张智倩王健
Owner FUDAN UNIV