Reusable model verification method for network interconnection chip

Abstract

The invention discloses a reusable model verification method for a network interconnection chip. The method comprises the steps of: in a model construction stage, distinguishing a chip model from an interconnection network model, carrying out description of a register level on an interface of the chip model according to a standard of actual RTL verification; setting up a simulation verification platform by utilizing the chip model and the interconnection network model, and carrying out model verification, wherein the simulation verification platform is configured according to the standard of actual RTL verification; and after completing an RTL code of the chip, replacing the chip model in the simulation verification platform with the RTL code of the chip, and reusing the simulation verification platform to carry out RTL verification. The method achieves improvement of a reusable degree of model verification, shortening of time of a verification period and improvement of verification efficiency.

Description

technical field [0001] The invention relates to the technical field of chip verification, in particular to a method for verifying a reusable model of a network interconnection chip. Background technique [0002] At present, with the continuous development of process technology and application fields, the complexity of chips continues to increase. Correspondingly, the complexity of verification work also continues to increase. The time spent on verification work has increasingly become the bottleneck of the chip development cycle. Therefore, how to carry out verification as early as possible and how to systematically carry out verification work to avoid repeated invalid verification work has become an important direction for optimizing chip verification work and shortening the chip development cycle. [0003] Generally, the use of model verification has become an inevitable choice for chip verification with complex logic. Model verification refers to the process of implement...

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Problems solved by technology

[0004] However, for the convenience of implementation, the model constructed purely by behavior-level description is very different from the actual RTL design in structure

The most obvious point is that the behavior-level model does not need to consider the problem of module division, and there will be no interface signals between corresponding RTL modules. The adverse effect brought about by this is the verification of the entire module including environment construction, system configuration, and test incentives. The re

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